Abstract. Writing an optimizing back end is expensive, in part because it requires mastery of both a target machine and a compiler’s internals. We separate these concerns by isolating target-machine knowledge in declarative machine descriptions. We then analyze these descriptions to automatically generate machinespecific components of the back end. In this work, we generate a recognizer; this component, which identifies register transfers that correspond to target-machine instructions, plays a key role in instruction selection in such compilers as vpo, gcc and Quick C--. We present analyses and transformations that address the major challenge in generating a recognizer: accounting for compile-time abstractions not present in a machine description, including variables, pseudo-registers, stack slots, and labels. 1

Optimal instruction scheduling and register allocation are NP-complete problems that require heuristic solutions. By restricting the problem of register allocation and instruction scheduling for delayed-load architectures to expression trees we are able to find optimal schedules quickly. This thesis presents a fast, optimal code scheduling algorithm for processors with a delayed load of 1 instruction cycle. The algorithm minimizes both execution time and register use and runs in time proportional to the size of the expression tree. In addition, the algorithm is simple

Many code generator generators use tree pattern matching and dynamic programming. This note describes a simple program that generates matchers that are fast, compact, and easy to understand. It is simpler than common alternatives: 200--700 lines of Icon versus 3000 lines of C for Twig and 5000 for burg. Its matchers run up to 25 times faster than Twig's. They are necessarily slower than burg's BURS (bottom-up rewrite system) matchers but they are more flexible and still practical. 1 AT&T Bell Laboratories, 600 Mountain Avenue 2C-464, Murray Hill, NJ 07974 2 Department of Computer Science, The University of Arizona, Tucson, AZ 85721 1 Introduction Many code generator generators use tree pattern matching and dynamic programming (DP) [3, 4]. They accept tree patterns and associated costs and semantic actions that, for example, allocate registers and emit object code. They produce tree matchers that make two passes over each subject tree. The first pass is bottom up and finds a set o...

Although I have proven that the general problem is undecidable, I show how, for machines of practical interest, to generate the back end of a compiler. Unlike previous work on generating back ends, I generate the machinedependent components of the back end using only information that is independent of the compiler’s internal data structures and intermediate form. My techniques substantially reduce the burden of retargeting the compiler: although it is still necessary to master the target machine’s instruction set, it is not necessary to master the data structures and algorithms in the compiler’s back end. Instead, the machine-dependent knowledge is isolated in the declarative machine descriptions. The largest machine-dependent component in a back end is the instruction selector. Previous work has shown that it is difficult to generate a highquality instruction selector. But by adopting the compiler architecture developed by Davidson and Fraser (1984), I can generate a naïve instruction

Code generation influences the efficiency of not only the compiled program but also the compilation process. The appearence of the many new processors has created the need of automating the code generation phase. The instruction selection is a important component to be poduced automatically in the code generation phase. The tools for automating the instruction selection usually use the tree-structure to represent the intermediate representation. The algorithms to manipulate the tree structure are simple. And the powerful tree rewriting tools can be automatically generated for transforming trees to target machine code. Among many technologies for the aumatic generation, BURS technology produces the fastest code generators. But, BURS technology often require long time and much space to process a complex machine description. Much efforts has gone to make BURS technology more attractive: efficient in points of time and space. In this proposal, we closely inspect BURS technology and propose...

Instruction selection is a key component of code generation. High quality instruction selection is of particular importance in the embedded space where complex instruction sets are common and code size is a prime concern. Although instruction selection on tree expressions is a well understood and easily solved problem, instruction selection on directed acyclic graphs is NP-complete. In this paper we present NOLTIS, a near-optimal, linear time instruction selection algorithm for DAG expressions. NOLTIS is easy to implement, fast, and effective with a demonstrated average code size improvement of 5.1 % compared to the traditional tree decomposition and tiling approach.

In an object-oriented database system (OODBS), objects exist persistently and object I/O is transparent to the programmer. Therefore, some mechanism in the system must initiate I/O as the program runs. In this paper we present an approach based on pattern matching and dynamic programming that allows a program to interact efficiently with the runtime storage layer. We are interested in allowing programs to manipulate very large objects without necessarily reading them entirely. If a program touches only a small part of a large object, the problem is how to determine the part of the object needed. In this paper, we present an approach based on pattern matching and dynamic programming to resolve this problem. We discuss and solve this problem in the context of VML, a modeling language of an open object-oriented database language. The VML compiler translates VML programs into C ++ programs which contain calls to the object manager. We provide a detailed description of our implementation ...

In this paper, we present an approach to handle the automatic generation of back-ends from a completely declarative specification of the target machine that does not require any knowledge of the code generation process. This paper mainly focuses on the various levels of intermediate representations used in a back-end based on the Pagode system. This approach has been validated by the production of a C-SPARC compiler. 1 Introduction High level languages and machine languages have different computation models. The compilation process can be split into several translation phases. Usually, a front-end translates the source program into an intermediate representation, the middle part works on the semantics and rearranges computations, translating to a lower level IR, and finally the back-end translates the last IR to actual target machine code. A back-end must not only map data access paths to hardware addressing modes, choose target machine instructions for IR code and allocate registers,...

Pagode is an advanced back-end generator that produces automatically a code generator from a specification of the processor. Such a specification is easy to derive from the various documents provided by the processor manufacturer, without requiring any additional code-generation expertise. This paper mainly focuses on the generic aspects of the Pagode system which is open enough to integrate the most powerful algorithms corresponding to the various subtasks of the code generation process. This approach has been validated by the production of a C-SPARC compiler in the framework of an industrial technology. Contents 1 Introduction 2 2 A generic back-end 3 3 Generic engines using the processor specification 4 3.1 The processor specification : : : : : : : : : : : : : : : : : : : : : : : : : : : : 4 3.2 A generic instruction selector : : : : : : : : : : : : : : : : : : : : : : : : : : : 7 3.3 A short example : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 7 3.4 The gen...

Compilers today are capable of inferring detailed information about program parallelism and analyzing whole-program behavior. However, the traditional interface between the compiler and the processor, as defined by the instruction set architecture (ISA), is unable to communicatemuch of the compiler knowledge to the processor. The approach taken by modern processors such as superscalars is to incorporate purely run-time algorithms in their hardware to perform analyses and optimizations such as detection of instruction-level parallelism. However, these complex hardware implementations can only exploit a small fraction of the parallelism information available to the compiler. The Raw architecture developed at MIT aims to maximally utilize the compiler by fully exposing the hardware and by delegating the hardware's control completely to the software system. The Raw microprocessor, a set of simple RISC-like processor tiles interconnected with a high-speed 2D mesh network, does not provide hardware implementations for any of the complex algorithms found in conventional microprocessors. Instead, the compiler and the run-time software system fully orchestrate the Raw hardware resources, and they implement run-time analyses and optimizations tailored to the need of each individual application. This novel approach provides many opportunities and challenges for the Raw compiler and run-time system. 1 1