Sorting networks of a fixed I/O size p have been used, thus far, for sorting a set of p elements. Somewhat surprisingly, the important problem of using such a sorting network for sorting arbitrarily large data sets has not been addressed in the literature. Our main contribution is to propose a simple sorting architecture whose main feature is the pipelined use of a sorting network of fixed I/O size p to sort an arbitrarily large data set of N elements. A noteworthy feature of our design is that no extra data memory space is required, other than what is used for storing the input. As it turns out, our architecture is feasible for VLSI implementation and its time performance is virtually independent of the cost and depth of the underlying sorting network. Specifically, we show that by using our design N elements can be sorted in ) time without memory access conflicts. Finally, we show how to use an AT -optimal sorting network of fixed I/O size p to construct a similar architecture that sorts N elements in Key Words: computer architecture, sorting, parallel processing, pipelined processing, sorting networks.

There has recently been an interest in the introduction of reconfigurable buses to existing parallel architectures. Among them the Reconfigurable Mesh (RM) draws much attention because of its simplicity. However the wide acceptance of RM depends on its scalability through self-simulation. This paper presents a simple self-simulation algorithm which can self-simulate the monotonic RM model optimally and the piecewise-monotonic RM model asymptotically optimally. We claim here that our algorithm preserves the essence of configurational computation and uses less broadcasts than simulation by the contraction and linear-connected component computation methods [1].

The k-merge problem, given a collection of k, (2 k n), sorted sequences of total length n, asks to merge them into a new sorted sequence. The main contribution of this work is to propose simple and intuitive work-time optimal algorithms for the k-merge problem on two PRAM models. Specifically, our k-merge algorithms perform O(n log k) work and run in O(log n) time on the EREW-PRAM and in O(log log n+log k) time on the CREW-PRAM, respectively. 1

In this paper we address a sparse matrix multiplication problem posed by Schmeck et al [6]. The main contribution is an optimal run-time algorithm for for multiplying a column sparse matrix by a row sparse matrix on the reconfigurable mesh architecture.

The recon#gurable mesh #rn-mesh#can solve a large class of problems in constant time, including problems that requirelogarithmic time by other, even shared memory, models such as the pram with a similar number of processors #3#. In this work we show that for the rn-mesh these constants can always bereduced to one, still using a polynomial number of processors. Given a recon#gurable mesh that computes a set of values in constant time, we show that it can be simulated by a single step recon#gurable mesh with maximum size that is polynomial in the size of the original mesh. The proof is constructive, where the construction of the single step rn-mesh holds for the relatively weak undirected rn-mesh model. In this model broadcasts made on buses arrive at all nodes that belong to the undirectedconnectedcomponent of the transmitting processor. A result similar to the one that is obtained in this work was previously obtained for the directedrecon #gurable mesh model #drn# #4#. However, the...

ABSTRACT Recently self-simulation algorithms have been developed to execute algorithms on a reconfigurable mesh (RM) of size smaller than recommended in those algorithms. Optimal slowdown, in self-simulation, has been achieved with the compromise that the resultant algorithms fail to remain AT 2 optimal. In this paper we introduce, for the first time, the idea of adaptive algorithm which runs on RM of variable sizes without compromising the AT 2 optimality. We support our idea by developing adaptive algorithms for sorting items and computing the contour of maximal elements of a set of planar points on RM.

Recently we have introduced the idea of adaptive algorithms which runs on reconfigurable meshes of variable sizes and aspect ratios without compromising AT² optimality. We have also supported our idea bydeveloping adaptive algorithms for sorting and computing maxima. In this paper we develop a new adaptive sorting algorithm which has lower constant associated with the highest order term in the complexityorder than our previously published adaptive sorting algorithm.

Sorting is a fundamental problem with applications in all areas of computer science and engineering. In this work we address the problem of sorting on mesh connected computers enhanced by endowing each row and each column with its own dedicated high-speed bus. This architecture, commonly referred to as a mesh with multiple broadcasting, is commercially available and has been adopted by the DAP family of multiprocessors. Somewhat surprisingly, the problem of sorting m, (m n), elements on a mesh with multiple broadcasting of size p n \Theta p n has been studied, thus far, only in the sparse case, where m 2 \Theta( p n) and in the dense case, where m 2 \Theta(n). Yet, many applications require using an existing platform of size p n \Theta p n for sorting m elements, with p n ! m n. Our main contribution is to present the first known adaptive time- and VLSI-optimal sorting algorithm for meshes with multiple broadcasting. Specifically, we show that for every choice of a constan...

Recently self-simulation algorithms have been developed to execute algorithms on a reconfigurable mesh (RM) of size smaller than recommended in those algorithms. Optimal slowdown, in self-simulation, has been achieved with the compromise that the resultant algorithms fail to remain AT 2 optimal. In this paper we introduce, for the first time, the idea of adaptive algorithm which runs on RM of variable sizes without compromising the AT 2 optimality. We support our idea by developing adaptive algorithms for sorting items and computing the contour of maximal elements of a set of planar points on RM. 1 INTRODUCTION It is well-known that interprocessor communications and simultaneous memory accesses often act as bottlenecks in present-day parallel machines. Bus systems have been introduced to a number of parallel computers [10, 11, 22] to address this problem. A bus system is called reconfigurable if it can be dynamically changed according to either global or local information. Introd...

Typeset in Palatino by TEX and LATEX 2ε.Except where otherwise indicated, this thesis is my own original work and has not been submitted for any other degree.