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Constant Time Algorithms for Computational Geometry on the Reconfigurable Mesh
 IEEE Transactions on Parallel and Distributed Systems
, 1997
"... The reconfigurable mesh consists of an array of processors interconnected by a reconfigurable bus system. The bus system can be used to dynamically obtain various interconnection patterns among the processors. Recently, this model has attracted a lot of attention. In this paper, we show O(1) time so ..."
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Cited by 18 (2 self)
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The reconfigurable mesh consists of an array of processors interconnected by a reconfigurable bus system. The bus system can be used to dynamically obtain various interconnection patterns among the processors. Recently, this model has attracted a lot of attention. In this paper, we show O(1) time solutions to the following computational geometry problems on the reconfigurable mesh: allpairs nearest neighbors, convex hull, triangulation, twodimensional maxima, twoset dominance counting, and smallest enclosing box. All these solutions accept N planar points as input and employ an N  N reconfigurable mesh. The basic scheme employed in our implementations is to recursively find an O(1) time solution. The number of recursion levels and the size of the subproblems at each level of recursion are optimized such that the problem decomposition and the solution to the problem can be obtained in constant time. As a result, we have developed some efficient merge techniques to combine th...
Reconfigurable Meshes: Theory and Practice
 In Reconfigurable Architectures Workshop, RAW'97
, 1997
"... Configurable computing has recently gained much attention with the promise of delivering an order of magnitude performance improvement over general purpose processors. In this paper we contrast the abstract models of reconfigurable architectures and actual hardware available for configurable computi ..."
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Cited by 10 (6 self)
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Configurable computing has recently gained much attention with the promise of delivering an order of magnitude performance improvement over general purpose processors. In this paper we contrast the abstract models of reconfigurable architectures and actual hardware available for configurable computing systems. There is a wealth of ideas related to abstract models of reconfigurable architectures and fast parallel algorithms which exploit the reconfiguration potential in nontrivial ways. We summarize these abstract models and illustrate the power of these models using several example algorithms. We identify the practical problems in implementing these models in VLSI and describe some prototype implementations. Commercial FPGA devices which are being touted as the solution for building configurable computing systems are also examined. The MAARC 2 project at USC endeavors to bridge this gap between the abstract and the real worlds. 1 This work was supported by DARPA under contract DABT...
Permutation routing and sorting on the reconfigurable mesh
 International Journal of Foundations of Computer Science
, 1992
"... Abstract In this paper we demonstrate the power of reconfiguration by presenting efficient randomized algorithms for both packet routing and sorting on a reconfigurable mesh connected computer. The run times of these algorithms are better than the best achievable time bounds on a conventional mesh. ..."
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Cited by 9 (3 self)
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Abstract In this paper we demonstrate the power of reconfiguration by presenting efficient randomized algorithms for both packet routing and sorting on a reconfigurable mesh connected computer. The run times of these algorithms are better than the best achievable time bounds on a conventional mesh. Many variations of the reconfigurable mesh can be found in the literature. We define yet another variation which we call as Mr. Wealsomakeuseofthestandard PARBUS model. We showthat permutation routing problem can be solved on a linear array Mr of size n in 3n steps, whereas n − 1 is the best possible run time without recon4 figuration. A trivial lower bound for routing on Mr will be n 2.OnthePARBUS linear array, n is a lower bound and hence any standard nstep routing algorithm will be optimal. We also showthat permutation routing on an n × n reconfigurable mesh Mr can be done in time n + o(n) using a randomized algorithm or in time 1.25n + o(n) deterministically. In contrast, 2n − 2 is the diameter of a conventional mesh and hence routing and sorting will need at least 2n−2 steps on a conventional mesh. A lower bound of n 2 is in effect for routing on the 2D mesh Mr as well. On the other 1 hand, n is a lower bound for routing on the PARBUS and our algorithms have the same time bounds on the PARBUS as well. Thus our randomized routing algorithm is optimal upto a lower order term. In addition we show that the problem of sorting can be solved in randomized time n + o(n) onMr as well as on PARBUS. Clearly, this sorting algorithm will be optimal on the PARBUS model. The time bounds of our randomized algorithms hold with high probability.
Efficient Self Simulation Algorithms for Reconfigurable Arrays
, 1995
"... There are several reconfiguringnetwork models of parallel computation that are considered in the published literature, depending on their switching capabilities. Can these reconfigurable models be the basis for the design of massively parallel computers? Perhaps the most fundamental related issue i ..."
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Cited by 7 (1 self)
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There are several reconfiguringnetwork models of parallel computation that are considered in the published literature, depending on their switching capabilities. Can these reconfigurable models be the basis for the design of massively parallel computers? Perhaps the most fundamental related issue is virtual parallelism, or the self simulation problem: given an algorithm which is designed for a large reconfigurable mesh, can it be executed efficiently on a smaller reconfigurable mesh? In this work we give several positive answers to the self simulation problem. We show that the simulation of a reconfiguring mesh by a smaller one can be carried optimally and using standard methods on the model in which buses are established along rows or along columns. A novel technique is shown to achieve asymptotically optimal self simulation on models which allow buses to switch column and row edges, provided that a bus is a "linear" path of connected edges. Finally, for models in which a bus is any ...
Algorithms for Optimal SelfSimulation of Some Restricted Reconfigurable Meshes
, 1997
"... There has recently been an interest in the introduction of reconfigurable buses to existing parallel architectures. Among them the Reconfigurable Mesh (RM) draws much attention because of its simplicity. However the wide acceptance of RM depends on its scalability through selfsimulation. This pa ..."
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Cited by 5 (3 self)
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There has recently been an interest in the introduction of reconfigurable buses to existing parallel architectures. Among them the Reconfigurable Mesh (RM) draws much attention because of its simplicity. However the wide acceptance of RM depends on its scalability through selfsimulation. This paper presents a simple selfsimulation algorithm which can selfsimulate the monotonic RM model optimally and the piecewisemonotonic RM model asymptotically optimally. We claim here that our algorithm preserves the essence of configurational computation and uses less broadcasts than simulation by the contraction and linearconnected component computation methods [1].
The Construction of Large Scale Reconfigurable Parallel Computing Systems (The Architecture of the SC320)
 International Journal of Foundations of Computer Science
, 1997
"... Reconfigurable communication networks for massively parallel multiprocessor systems offer the possibility to realize a number of application demands like special communication patterns or realtime requirements. This paper presents the design principle of a reconfigurable network which is able to re ..."
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Cited by 1 (1 self)
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Reconfigurable communication networks for massively parallel multiprocessor systems offer the possibility to realize a number of application demands like special communication patterns or realtime requirements. This paper presents the design principle of a reconfigurable network which is able to realize any graph of maximal degree four. The architecture is based on a special multistage Clos network, constructed out of a number of static routing switches of equal size. Upper bounds on the cut size of 4regular graphs, if split into a number of clusters, allow minimizing the number of switches and connections while still offering the desired reconfiguration capabilities as well as large scalability and flexible multiuser access. Efficient algorithms configuring the architecture are based on an old result by Petersen 27 about the decomposition of regular graphs. The concept presented here is the basis for the Parsytec SC series of reconfigurable MPPsystems. The currently largest reali...
ApplicationSpecific Array Processors for Binary Prefix Sum Computation
"... The main contribution of this work is to propose two applicationspecific bus architectures for computing the prefi sums of a binary sequence. Our architectures feature the following characteristics: (1) all broadcasts occur on buses of length I5 or 63; (2) we use a new technique tha ~ we call shift ..."
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The main contribution of this work is to propose two applicationspecific bus architectures for computing the prefi sums of a binary sequence. Our architectures feature the following characteristics: (1) all broadcasts occur on buses of length I5 or 63; (2) we use a new technique tha ~ we call shift switching which allows switches to cyclically permute an incoming signul, dramatically improving the performance of the reconfigurable bus system. As it turns out, our specialpurpose architectures improve the performance of the best algorithm known to date by a significant factor. Specifically, our solutions require no adders, are faster, and use less VLSI area than the architectures of the state of the art. 1.
Mesh with Applications to Prefix Sums and Approximate String Matching
"... numbers as moduli and are suited for parallel computations on a reconfigurable mesh architecture. The bit model of linear reconfigurable mesh with exclusive write and unittime delay for broadcasting on a subbus is assumed. It is shown how to convert in O…1 † time any integer, ranging between 0 andn ..."
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numbers as moduli and are suited for parallel computations on a reconfigurable mesh architecture. The bit model of linear reconfigurable mesh with exclusive write and unittime delay for broadcasting on a subbus is assumed. It is shown how to convert in O…1 † time any integer, ranging between 0 andn 1, from any commonly used representation to any new representation proposed in this paper (and vice versa) using an n O log2n log logn reconfigurable mesh. In particular, some of the previously known conversion techniques are improved. Moreover, as a byproduct, it is shown how to compute in O…1 † time the Prefix Sums of n bits by a reconfigurable mesh having the above mentioned size, thus improving previously known results. Applications to the Prefix Sums of N hbit integers and to Approximate String Matching with mismatches are also considered. The Summation and the Prefix Sums can be computed inO…1 † time usingOhlogN ‡ log2N log logN Nh andO h2 ‡log 2 N log…h‡logN † O…N…h ‡ logN† † reconfigurable meshes, respectively. Moreover, it is shown for the first time how to find inO…1 † time all the occurrences of a pattern of lengthmin a text of lengthn, allowing less than mismatches, using a reconfigurable mesh of sizeO…m log j j † On log j j ‡ log2 log log, where the pattern and the text are strings over a finite alphabet and <m n. Index TermsÐNumber representation, prefix sums, reconfigurable mesh, residue number system, string matching withkmismatches, VLSI. 1
The Reconfigurable Mesh: Programming Model, SelfSimulation, Adaptability, Optimality, and Applications
"... Typeset in Palatino by TEX and LATEX 2ε.Except where otherwise indicated, this thesis is my own original work and has not been submitted for any other degree. ..."
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Typeset in Palatino by TEX and LATEX 2ε.Except where otherwise indicated, this thesis is my own original work and has not been submitted for any other degree.