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Mesh Connected Computers with Fixed and Reconfigurable Buses: Packet Routing, Sorting, and Selection
 In proc. 1st European Symp. on Algorithms
, 1993
"... Mesh connected computers have become attractive models of computing because of their varied special features. In this paper we consider two variations of the mesh model: 1) a mesh with fixed buses, and 2) a mesh with reconfigurable buses. Both these models have been the subject matter of extensive p ..."
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Cited by 25 (10 self)
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Mesh connected computers have become attractive models of computing because of their varied special features. In this paper we consider two variations of the mesh model: 1) a mesh with fixed buses, and 2) a mesh with reconfigurable buses. Both these models have been the subject matter of extensive previous research. We solve numerous important problems related to packet routing, sorting, and selection on these models. In particular, we provide lower bounds and very nearly matching upper bounds for the following problems on both these models: 1) Routing on a linear array; and 2) k \Gamma k routing and k \Gamma k sorting on a 2D mesh for any k 12. We provide an improved algorithm for 1 \Gamma 1 routing and a matching sorting algorithm. In addition we present greedy algorithms for 1 \Gamma 1 routing, k \Gamma k routing, and k \Gamma k sorting that are better on average and supply matching lower bounds. We also show that sorting can be performed in logarithmic time on a mesh with fixed bu...
Image Processing On The OTISMesh Optoelectronic Computer
 IEEE Transactions on Parallel and Distributed Systems
, 2000
"... We develop algorithms for histogramming, histogram modification, Hough transform, and image shrinking and expanding on an OTISMesh optoelectronic computer. Our algorithm for the Hough transform is based upon a mesh algorithm for the Hough transform which is also developed in this paper. This new me ..."
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Cited by 22 (2 self)
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We develop algorithms for histogramming, histogram modification, Hough transform, and image shrinking and expanding on an OTISMesh optoelectronic computer. Our algorithm for the Hough transform is based upon a mesh algorithm for the Hough transform which is also developed in this paper. This new mesh algorithm improves upon the mesh Hough transform algorithms of [4] and [14].
Sorting and Selection on Interconnection Networks
 DIMACS Series in Discrete Mathematics and Theoretical Computer Science
, 1995
"... ABSTRACT. In this paper we identify techniques that havebeen employed in the design of sorting and selection algorithms for various interconnection networks. We consider both randomized and deterministic techniques. Interconnection Networks of interest include the mesh, the mesh with xed and recon g ..."
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Cited by 21 (15 self)
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ABSTRACT. In this paper we identify techniques that havebeen employed in the design of sorting and selection algorithms for various interconnection networks. We consider both randomized and deterministic techniques. Interconnection Networks of interest include the mesh, the mesh with xed and recon gurable buses, the hypercube family, and the star graph. For the sake of comparisons, we also list PRAM algorithms. 1
Constant Time Algorithms for Computational Geometry on the Reconfigurable Mesh
 IEEE Transactions on Parallel and Distributed Systems
, 1997
"... The reconfigurable mesh consists of an array of processors interconnected by a reconfigurable bus system. The bus system can be used to dynamically obtain various interconnection patterns among the processors. Recently, this model has attracted a lot of attention. In this paper, we show O(1) time so ..."
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Cited by 18 (2 self)
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The reconfigurable mesh consists of an array of processors interconnected by a reconfigurable bus system. The bus system can be used to dynamically obtain various interconnection patterns among the processors. Recently, this model has attracted a lot of attention. In this paper, we show O(1) time solutions to the following computational geometry problems on the reconfigurable mesh: allpairs nearest neighbors, convex hull, triangulation, twodimensional maxima, twoset dominance counting, and smallest enclosing box. All these solutions accept N planar points as input and employ an N  N reconfigurable mesh. The basic scheme employed in our implementations is to recursively find an O(1) time solution. The number of recursion levels and the size of the subproblems at each level of recursion are optimized such that the problem decomposition and the solution to the problem can be obtained in constant time. As a result, we have developed some efficient merge techniques to combine th...
Computer Vision Algorithms on Reconfigurable Logic Arrays
 IEEE TRANS. ON PARALLEL AND DISTRIBUTED SYSTEMS
, 1999
"... Computer vision algorithms are natural candidates for high performance computing due to their inherent parallelism and intense computational demands. For example, a simple 3 x 3 convolution on a 512 x 512 gray scale image at 30 frames per second requires 67.5 million multiplications and 60 million a ..."
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Cited by 15 (1 self)
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Computer vision algorithms are natural candidates for high performance computing due to their inherent parallelism and intense computational demands. For example, a simple 3 x 3 convolution on a 512 x 512 gray scale image at 30 frames per second requires 67.5 million multiplications and 60 million additions to be performed in one second. Computer vision tasks can be classified into three categories based on their computational complexity andcommunication complexity: lowlevel, intermediatelevel and highlevel. Specialpurpose hardware provides better performance compared to a generalpurpose hardware for all the three levels of vision tasks. With recent advances in very large scale integration (VLSI) technology, an application specific integrated circuit (ASIC) can provide the best performance in terms of total execution time. However, long design cycle time, high development cost and inflexibility of a dedicated hardware deter design of ASICs. In contrast, field programmable gate arrays (FPGAs) support lower design verification time and easier design adaptability atalower cost. Hence, FPGAs with an array of reconfigurable logic blocks canbevery useful compute elements. FPGAbased custom computing machines are
Selection on the Reconfigurable Mesh
 Proc. Frontiers of Massively Parallel Computation
, 1992
"... Our main result is a \Theta(log n) time algorithm to select the kth smallest element in a set of n elements on a reconfigurable mesh with n processors. This improves on the previous fastest algorithm's running time by a factor of log n. We also show that some variants of this problem can be solved e ..."
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Cited by 14 (0 self)
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Our main result is a \Theta(log n) time algorithm to select the kth smallest element in a set of n elements on a reconfigurable mesh with n processors. This improves on the previous fastest algorithm's running time by a factor of log n. We also show that some variants of this problem can be solved even faster. First we show that a good approximation to the median of n elements can be found in \Theta(log log n) time. This can be used to solve twodimensional linear programming over n equations in \Theta(log n log log n) time, an improvement of log n= log log n time over the previous fastest algorithm. Next, we show that, for any constant ffl ? 0, selecting the kth smallest element in a set of n 1\Gammaffl elements evenly spaced throughout the mesh can be done in constant time. We also show that one can select the kth smallest element from n bbit words in \Theta((b= log b) maxflog n \Gamma log b; 1g) time, which implies that if the elements come from a polynomial range, one can...
An Optimal Multiplication Algorithm on Reconfigurable Mesh
 IEEE Transactions on Parallel and Distributed Systems
, 1997
"... An O(1) time algorithm to multiply two Nbit binary numbers using an N N bitmodel of reconfigurable mesh is shown. It uses optimal mesh size and it improves previously known results for multiplication on the reconfigurable mesh. The result is obtained by using novel techniques for data representat ..."
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Cited by 13 (3 self)
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An O(1) time algorithm to multiply two Nbit binary numbers using an N N bitmodel of reconfigurable mesh is shown. It uses optimal mesh size and it improves previously known results for multiplication on the reconfigurable mesh. The result is obtained by using novel techniques for data representation and data movement and using multidimensional Rader Transform. The algorithm is extended to result in AT 2 optimality over 1 TN in a variant of the bitmodel of VLSI. Index TermsInteger multiplication, reconfigurable mesh, optimal algorithm, areatime trade off, VLSI architecture.  F  1I NTRODUCTION HE reconfigurable mesh is a twodimensional mesh of processors connected by reconfigurable buses [17]. Though the buses outside the Processing Elements (PEs) are fixed, the internal connection between the I/O ports of each PE can be reconfigured by individual PEs during the execution of algorithms. The reconfigurable mesh cap...
On the Power of Arrays with Reconfigurable Optical Buses
, 1996
"... This paper examines some computational aspects of different arrays enhanced with optical pipelined buses. The array processors with optical pipelined buses (APPB) are shown to be extremely flexible, as demonstrated by their ability to efficiently simulate different variants of PRAMs and bounded degr ..."
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Cited by 13 (2 self)
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This paper examines some computational aspects of different arrays enhanced with optical pipelined buses. The array processors with optical pipelined buses (APPB) are shown to be extremely flexible, as demonstrated by their ability to efficiently simulate different variants of PRAMs and bounded degree networks. A model of computation is introduced, the array with reconfigurable optical buses (AROB), which combines some of the advantages and characteristics of the classical reconfigurable networks (RN) and the APPB. A number of applications of the APPB and AROB are presented, and their power is investigated. It is shown that beside AROB's capability of simulating classical reconfigurable networks, the enhanced communication mechanisms allow for an important system reduction when compared with the classical RNs. Keywords: optical interconnections, pipelined optical buses, reconfigurable networks, bounded degree networks, PRAM models. 1 Introduction Interprocessor communication networks...
Routing and Sorting on Meshes with Row and Column Buses
, 1994
"... of the 27th Annual IEEE Symposium on Foundations of Computer Science, pages 264273, 1986. [50] T. Suel. Routing and sorting on meshes with row and column buses. In Proceedings of the 8th International Parallel Processing Symposium, April 1994. [51] B. Wang and G. Chen. Constant time algorithms fo ..."
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Cited by 13 (1 self)
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of the 27th Annual IEEE Symposium on Foundations of Computer Science, pages 264273, 1986. [50] T. Suel. Routing and sorting on meshes with row and column buses. In Proceedings of the 8th International Parallel Processing Symposium, April 1994. [51] B. Wang and G. Chen. Constant time algorithms for the transitive closure and some related graph problems on processor arrays with reconfigurable bus systems. IEEE Transactions on Parallel and Distributed Systems, 1:500507, 1990. [27] M. Kunde. Block gossiping on grids and tori: Deterministic sorting and routing match the bisection bound. In Proceedings of the 1st Annual European Symposium on Algorithms, September 1993. [28] R. E. Ladner, J. Lampe, and R. Rogers. Vector prefix addition on subbus mesh computers. In Proceedings of the 5th Annual ACM Symposium on Parallel Algorithms and Architectures, pages 387396, June 1993. [29] F. T. Leighton. Tight bounds on the com
Reconfigurable Meshes: Theory and Practice
 In Reconfigurable Architectures Workshop, RAW'97
, 1997
"... Configurable computing has recently gained much attention with the promise of delivering an order of magnitude performance improvement over general purpose processors. In this paper we contrast the abstract models of reconfigurable architectures and actual hardware available for configurable computi ..."
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Cited by 10 (6 self)
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Configurable computing has recently gained much attention with the promise of delivering an order of magnitude performance improvement over general purpose processors. In this paper we contrast the abstract models of reconfigurable architectures and actual hardware available for configurable computing systems. There is a wealth of ideas related to abstract models of reconfigurable architectures and fast parallel algorithms which exploit the reconfiguration potential in nontrivial ways. We summarize these abstract models and illustrate the power of these models using several example algorithms. We identify the practical problems in implementing these models in VLSI and describe some prototype implementations. Commercial FPGA devices which are being touted as the solution for building configurable computing systems are also examined. The MAARC 2 project at USC endeavors to bridge this gap between the abstract and the real worlds. 1 This work was supported by DARPA under contract DABT...