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3D ICs: A Novel Chip Design for Improving DeepSubmicrometer Interconnect Performance and SystemsonChip Integration
 Proceedings of the IEEE
, 2001
"... This paper analyzes the limitations of the existing interconnect technologies and design methodologies and presents a novel threedimensional (3D) chip design strategy that exploits the vertical dimension to alleviate the interconnect related problems and to facilitate heterogeneous integration of ..."
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Cited by 161 (16 self)
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This paper analyzes the limitations of the existing interconnect technologies and design methodologies and presents a novel threedimensional (3D) chip design strategy that exploits the vertical dimension to alleviate the interconnect related problems and to facilitate heterogeneous integration of technologies to realize a systemonachip (SoC) design. A comprehensive analytical treatment of these 3D ICs has been presented and it has been shown that by simply dividing a planar chip into separate blocks, each occupying a separate physical level interconnected by short and vertical interlayer interconnects (VILICs), significant improvement in performance and reduction in wirelimited chip area can be achieved, without the aid of any other circuit or design innovations. A scheme to optimize the interconnect distribution among different interconnect tiers is presented and the effect of transferring the repeaters to upper Si layers has been quantified in this analysis for a twolayer 3D
Energy Efficient CMOS Microprocessor Design
 PROCEEDINGS OF THE 28TH ANNUAL HAWAII INTERNATIONAL CONFERENCE ON SYSTEM SCIENCES
, 1995
"... Reduction of power dissipation in microprocessor design is becoming a key design constraint. This is motivated not only by portable electronics, in which battery weight and size is critical, but by heat dissipation issues in larger desktop and parallel machines as well. By identifying the major mode ..."
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Cited by 159 (4 self)
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Reduction of power dissipation in microprocessor design is becoming a key design constraint. This is motivated not only by portable electronics, in which battery weight and size is critical, but by heat dissipation issues in larger desktop and parallel machines as well. By identifying the major modes of computation of these processors and by proposing figures of merit for each of these modes, a power analysis methodology is developed. It allows the energy efficiency of various architectures to be quantified, and provides techniques for either individually optimizing or trading off throughput and energy consumption. The methodology is then used to qualify three important design principles for energy efficient microprocessor design.
Processor Design for Portable Systems
 Journal of VLSI Signal Processing
, 1996
"... : Processors used in portable systems must provide highly energyefficient operation, due to the importance of battery weight and size, without compromising high performance when the user requires it. The userdependent modes of operation of a processor in portable systems are described and separate ..."
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Cited by 93 (1 self)
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: Processors used in portable systems must provide highly energyefficient operation, due to the importance of battery weight and size, without compromising high performance when the user requires it. The userdependent modes of operation of a processor in portable systems are described and separate metrics for energy efficiency for each of them are found to be required. A variety of well known lowpower techniques are reevaluated against these metrics and in some cases are not found to be appropriate leading to a set of energyefficient design principles. Also, the importance of idle energy reduction and the joint optimization of hardware and software will be examined for achieving the ultimate in lowenergy, highperformance design. 1. Introduction The recent explosive growth in portable electronics requires energy conscious design, without sacrificing performance. Simply increasing the battery capacity is not sufficient because the battery has become a significant fraction of the t...
Optimal Design of a CMOS OpAmp via Geometric Programming
"... We describe a new method for determining component values and transistor dimensions for CMOS operational amplifiers (opamps). We observe that a wide variety of design objectives and constraints have a special form, i.e., theyareposynomial functions of the design variables. As a result the amplifi ..."
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Cited by 85 (9 self)
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We describe a new method for determining component values and transistor dimensions for CMOS operational amplifiers (opamps). We observe that a wide variety of design objectives and constraints have a special form, i.e., theyareposynomial functions of the design variables. As a result the amplifier design problem can be expressed as a special form of optimization problem called geometric programming, for which very efficient global optimization methods have been developed. As a consequence we can efficiently determine globally optimal amplifier designs, or globally optimal tradeoffs among competing performance measures such as power, openloop gain, and bandwidth. Our method therefore yields completely automated synthesis of (globally) optimal CMOS amplifiers, directly from specifications. In this paper we apply this method to a specific, widely used operational amplifier architecture, showing in detail how to formulate the design problem as a geometric program. We compute globally optimal tradeoff curves relating performance measures such as power dissipation, unitygain bandwidth, and openloop gain. We show how the method can be used to synthesize robust designs, i.e., designs guaranteed to meet the specifications for a variety of process conditions and parameters.
Low Power Architectural Design Methodologies
 PH.D THESIS, MEMORANDUM NO. UCB/ERL M94/62, 30TH
, 1994
"... In recent years, power consumption has become a critical design concern for many VLSI systems. Nowhere is this more true than for portable, batteryoperated applications, where power consumption has perhaps superceded speed and area as the overriding implementation constraint. This adds another de ..."
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Cited by 19 (0 self)
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In recent years, power consumption has become a critical design concern for many VLSI systems. Nowhere is this more true than for portable, batteryoperated applications, where power consumption has perhaps superceded speed and area as the overriding implementation constraint. This adds another degree of freedom  and complexity  to the design process and mandates the need for design techniques and CAD tools that address power, as well as area and speed. This thesis presents a methodology and a set of tools that support lowpower system design. Lowpower techniques at levels ranging from technology to architecture are presented and their relative merits are compared. Several case studies demonstrate that architecture and systemlevel optimizations offer the greatest opportunities for power reduction. A survey of existing power analysis tools, however, reveals a marked lack of powerconscious tools at these levels. Addressing this issue, a collection of techniques for modeling power at the registertransfer (RT) level of abstraction is described. These techniques model the impact of design complexity and signal activity on datapath, memory, control, and interconnect power consumption. Several VLSI design examples are used to verify the proposed tools, which exhibit near switchlevel accuracy at RTlevel speeds. Finally, an integrated design space exploration environment is described that spans several levels of abstraction and embodies many of the power optimization and analysis strategies presented in this thesis.
Overview of Nanoelectronic Devices
 Proceedings of the IEEE
, 1997
"... This paper provides an overview of research developments toward nanometerscale electronic switching devices for use in building ultradensely integrated electronic computers. Specifically, two classes of alternatives to the fieldeffect transistor are considered: 1) quantumeffect and singleelectr ..."
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Cited by 17 (1 self)
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This paper provides an overview of research developments toward nanometerscale electronic switching devices for use in building ultradensely integrated electronic computers. Specifically, two classes of alternatives to the fieldeffect transistor are considered: 1) quantumeffect and singleelectron solidstate devices and 2) molecular electronic devices. A taxonomy of devices in each class is provided, operational principles are described and compared for the various types of devices, and the literature about each is surveyed. This information is presented in nonmathematical terms intended for a general, technically interested readership
The twintransistor noisetolerant dynamic circuit technique
 IEEE J. SolidState Circuits
, 2001
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LowVoltage CMOS Circuits for Analog Iterative Decoders
 IEEE TRANS. CIRCUITS AND SYSTEMS I: REGULAR PAPERS
, 2006
"... Iterative decoders, including Turbo decoders, provide nearoptimal error protection for various communication channels and storage media. CMOS analog implementations of these decoders offer dramatic savings in complexity and power consumption, compared to digital architectures. Conventional CMOS an ..."
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Cited by 14 (3 self)
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Iterative decoders, including Turbo decoders, provide nearoptimal error protection for various communication channels and storage media. CMOS analog implementations of these decoders offer dramatic savings in complexity and power consumption, compared to digital architectures. Conventional CMOS analog decoders must have supply voltage greater than 1 V. A new lowvoltage architecture is proposed which reduces the required supply voltage by at least 0.4 V. It is shown that the lowvoltage architecture can be used to implement the general sumproduct algorithm. The lowvoltage analog architecture is then useful for implementing Turbo and lowdensity parity check decoders. The lowvoltage architecture introduces new requirements for signal normalization, which are discussed. Measured results for two fabricated lowvoltage analog decoders are also presented.