For circuits of VLSI complexity, test generation time can be prohibitive. Most of the time is consumed by hard-to-detect (HTD) faults which might remain undetected even after a large number of backtracks. We identify the problems inherent in a uniprocessor implementation of a test generation algorithm and propose a parallel test generation algorithm which tries to achieve a high fault coverage for HTD faults in a reasonable amount of time. A dynamic search space allocation strategy is used which ensures that the search spaces allocated to different processors are disjoint. The parallel test generation algorithm has been implemented on an Intel iPSC/2 hypercube. Results are presented using the ISCAS combinational benchmark circuits which conclusively prove that parallel processing of HTD faults does indeed result in high fault coverage which is otherwise not achievable by a uniprocessor algorithm in limited CPU time. The parallel algorithm exhibits superlinear speedups in some cases due...

Abstract—At-speed functional testing, delay testing, and n-detection test sets are being used today to detect deep submicrometer defects. However, the resulting test data volumes are too high; the 2005 International Roadmap for Semiconductors predicts that test-application times will be 30 times larger in 2010 than they are today. In addition, many new types of defects cannot be accurately modeled using existing fault models. Therefore, there is a need to model the quality of test patterns such that they can be quickly assessed for defect screening. Test selection is required to choose the most effective pattern sequences from large test sets. Current industry practice for test selection is based on fault grading, which is computationally expensive and must also be repeated for every fault model. Moreover, although efficient methods exist today, for fault-oriented test generation, there is a lack of understanding on how best to combine the test sets thus obtained, i.e., derive the most effective union of the individual test sets without simply taking all the patterns for each fault model. This paper presents the use of the output deviation as a surrogate coverage-metric for pattern modeling and test grading. A flexible, but general, probabilistic-fault model is used to generate a probability map for the circuit, which can subsequently be used for test-pattern reordering. The output deviations resulting from the probability map(s) are used as a coverage-metric to model test patterns; the higher the deviation, the better the quality of the test pattern. We show that, for the ISCAS benchmark circuits and as compared to other reordering methods, the proposed method provides “steeper ” coverage curves for different fault models. Index Terms—Abort-on-first-fail, defect coverage, testapplication time, test-pattern grading, test selection. I.

A new approach to optimize multilevel logic circuits is introduced. Given a multilevel circuit, the synthesis method optimizes its area while simultaneously enhancing its random pattern testability. The method is based on structural transformations at the gate level. New transformations involving EX-OR gates as well as Reed--Muller expansions have been introduced in the synthesis of multilevel circuits. This method is augmented with transformations that specifically enhance random-pattern testability while reducing the area. Testability enhancement is an integral part of our synthesis methodology. Experimental results show that the proposed methodology not only can achieve lower area than other similar tools, but that it achieves better testability compared to available testability enhancement tools such as tstfx. Specifically for ISCAS-85 benchmark circuits, it was observed that EX-OR gate-based transformations successfully contributed toward generating smaller circuits compared to other state-ofthe -art logic optimization tools.

In this paper we present a fast algorithm for evaluating the arithmetic transform of a Boolean function based on its circuit representation. The arithmetic transform has multiple applications in CAD, including the computation of signal probabilities and switching activities of circuit nets and the mapping of Boolean functions onto probabilistic hash values. Previous algorithms for evaluating the arithmetic transform required an orthogonal, nonredundant representation of the function to be transformed in form of a disjoint function cover or a single BDD. We present a new algorithm that partitions the evaluation based on the dominator relations of the circuit graph. Similar to the application of cut-points in combinational equivalence checking, the dominators are used to progressively simplify intermediate evaluation steps. As a result, the presented algorithm can handle larger circuits than previously possible. An extensive set of experiments on benchmark and industrial circuits demonstrate the effectiveness of our approach.

Methods based on AND/OR graph representations of Boolean relations provide a promising new way of approaching VLSI CAD design automation problems. AND/OR graphs can represent any Boolean network and they allow for systematic reasoning through the application of the technique of recursive learning. An approach to build and analyze AND/OR graphs that makes use of hashing techniques in a way similar to that for modern Decision Diagram (DD) packages is described. Additionally, the problem of extracting spectral information from AND/OR graphs is also examined. Spectral information can be used for many CAD system tasks including synthesis, verification and test vector generation. It is shown that spectral information may be calculated directly from output probabilities and a method for estimating output probabilities from AND/OR graphs is presented. Experimental results regarding the AND/OR graph package efficiency and the extraction of spectral information are provided. 1 Introdu...

STAFAN (Statistical Fault Analysis) is a well known testability analysis program which predicts the fault coverage of a digital circuit under the stuck-at fault model, without actually performing fault simulation. STAFAN offers speed advantage over other testability analysis programs such as SCOAP; further, it explicitly predicts the fault coverage for a given test set, unlike other testability measures which are harder to interpret. STAFAN works on gate-level digital circuits composed of basic logic gates. In this work, we show how a STAFAN-like testability analysis program can be constructed for circuits built out of register-level modules. With the proliferation of high-level synthesis and testability-driven synthesis, it is becoming more and more important to have fast testability analysis tools which operate on register-level components such as adders, multipliers, multiplexers, busses, and so on. Our testability analysis algorithm, which we call F-STAFAN, fills this void. We have implemented F-STAFAN on a Sun/SPARC workstation and describe its performance on several register-level circuits. 1

Abstract—To predict the difficulty of testing a wire stuck-at fault, testability analysis algorithms provide an estimated testability value by computing controllability and observability. In most common previous work such as COP and SCOAP, signal correlation between controllability and observability is not well handled. As a result, the estimated values can be quite inaccurate. On the other hand, some previous work can take into account signal correlation but may require more CPU time. This paper discusses an efficient method for testability analysis improvement. Our algorithm starts with results obtained from conventional testability analysis such as COP. For each stuck- at fault, we gradually refine these results by recursively applying some simple signal correlation rules. Experimental results show that, with reasonable run-time overhead, significant improvement for testability analysis can be achieved. Index Terms—COP, implication, SCOAP, testability, testing. I.

Towards predictable deep-submicron manufacturing

The history of semiconductor chips has been characterized by a steady growth in the level of integration. Although this growth has given computer designers more capable circuits, it has become increasingly difficult to ensure highly reliable designs. Until now, the reliability of semiconductor chips has been parametrized by the logic family; the operating voltage, temperature, and environment; and the level of integration of the component. Thus, to obtain highly reliable systems, it was often necessary to limit the number of transistors. An attractive and potentially important extension to the analysis of circuit reliability is to account for the connectivity of the individual internal components. For circuits in Complementary Metal Oxide Silicon (cmos) technology, this reliability analysis is accomplished by modeling open and shorted transistors, "stuck--at" wires, and failed power and ground sources. Direct analysis of the reliability of a circuit by exhaustive enumeration of all fau...

This dissertation addresses the problem of capturing the dynamic communication in VLSI circuits. There are several CAD problems where attributes that combine behavior and structure are needed, or when function behavior is too complex and is best captured through some attribute in the implementation. Examples include, timing analysis, logic synthesis, dynamic power estimation, and variable ordering for binary decision diagrams (BDDs). In such a situation, using static attributes computed from the structure of the implementation is not always helpful. Firstly, they do not provide sufficient usage information, and secondly they tend to exhibit variances with implementations which is not desirable while capturing function behavior. The contribution of this research is a new circuit attribute called spatial entropy. It models the dynamic communication effort in the circuit by unifying the static structure and the dynamic data usage. Quantitatively, spatial entropy measures the switching en...