Low power has emerged as a principal theme in today's electronics industry. The need for low power has caused a major paradigm shift in which power dissipation is as important as performance and area. This article presents an in-depth survey of CAD methodologies and techniques for designing low power digital CMOS circuits and systems and describes the many issues facing designers at architectural, logic and physical levels of design abstraction. It reviews some of the techniques and tools that have been proposed to overcome these difficulties and outlines the future challenges that must be met to design low power, high performance systems.

Reliability assessment is an important part of the design process of digital integrated circuits. We observe that a common thread that runs through most causes of run-time failure is the extent of circuit activity, i.e., the rate at which its nodes are switching. We propose a new measure of activity, called the transition density, which may be defined as the "average switching rate" at a circuit node. Based on a stochastic model of logic signals, we also present an algorithm to propagate density values from the primary inputs to internal and output nodes. To illustrate the practical significance of this work, we demonstrate how the density values at internal nodes can be used to study circuit reliability by estimating (1) the average power & ground currents, (2) the average power dissipation, (3) the susceptibility to electromigration failures, and (4) the extent of hot-electron degradation. The density propagation algorithm has been implemented in a prototype density simulator. Using ...

A novel current-estimation approach is developed to support the analysis of electromigration failures in power supply and ground busses of CMOS VLSI circuits. It uses the original concept of probabilistic simulation to efficiently generate accurate estimates of the expected current waveform required for electromigration analysis. As such, the approach is pattern-independent and relieves the designer of the tedious task of specifying logical input waveforms. This approach has been implemented in the program CREST which has shown excellent accuracy and dramatic speedups compared to traditional approaches. We describe the approach and its implementation, and present the results of numerous CREST runs on real circuits. F. Najm is now with the VLSI Design Laboratory, Texas Instruments Inc., Dallas, Texas 75265 This work was supported by Texas Instruments Incorporated, and the US Air Force Rome Air Development Center. 1 Introduction The reliability of integrated circuits is a major conc...

This work presents techniques for computing the switching activities of all circuit nodes under pseudorandom or biased input sequences and assuming a zero delay mode of operation. Complex spatiotemporal correlations among the circuit inputs and internal nodes are considered by using a lag-one Markov Chain model. Evaluations of the model and a comparative analysis presented for benchmark circuits demonstrates the accuracy and the practicality of the method. The results presented in this paper are useful in power estimation and low power design. 1. Introduction In estimating the power consumption in a digital circuit, knowledge about the average switching activity in the circuit plays a significant part because most of the power in CMOS circuits is consumed during charging and discharging of the load capacitance. To estimate the power consumption, one has to calculate the switching activity factors of the internal nodes of the circuit. The key issue in switching activity estimation is ...

Accurate and efficient expected current estimation is required in circuit designs to analyze electromigration failure rate, power consumption, voltage drop, etc. A new patternindependent simulation approach for estimating this expected current waveform drawn by CMOS circuitry has been developed. Four original concepts, probability waveforms, probability waveform propagation, probabilistic circuit models, and statistical timing analysis, are presented which allows an efficient and accurate estimation of expected current waveforms. This approach is dramatically faster than traditional methods and yields comparable results. Topics : 1, 16, 12. I. INTRODUCTION The quality of an integrated circuit is measured by both functional and reliability standards. Many simulation approaches exist to verify that a design will meet functional specifications; however, present capabilities for verifying that a design will meet reliability specifications are extremely limited. At Texas Instruments, much...

: Excessive power supply and ground currents in integrated circuits can severely affect circuit reliability and performance. Some of the problems arising from excessive current flow are : (1) excessive voltage drop (glitches) on the power/ground lines, which can lead to soft errors, and (2) large instantaneous power dissipation, which causes overheating and ultimately leads to performance degradation. Maximum current estimates are, therefore, needed in the supply lines in order to determine the severity of these problems. These currents, however, depend on the specific input patterns that are applied to the circuit. Most previous work in this area has focused on search techniques that attempt to locate the worst case current by searching for the corresponding worst case input patterns. However, since the input space is huge, search-based algorithm for this problem can take an exponential amount of time, in the worst case. In this paper, we propose a pattern-independent, linear-time alg...

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Switching activity estimation in combinational circuits is addressed from a probabilistic point of view. The zero-delay hypothesis is considered and under pseudorandom or biased input sequences, the activities at the primary outputs and all internal nodes are estimated. Work by previous researchers is extended to manage complex spatio-temporal correlations by using lag-one Markov Chains and conditional probabilities. Evaluations of the model and a comparative analysis presented for benchmark circuits demonstrates the accuracy and the practicality of the method. The results presented in this paper are useful in power estimation and low power design. 1. Introduction In solving the complex problem of power estimation for digital circuits, knowledge about the average switching activity in a circuit plays a significant part. Indeed, to compute the power dissipation, most of the current models rely on the switching activity information about the circuit. The accuracy in making such estimat...

In recent years, power consumption has become a critical design concern for many VLSI systems. Nowhere is this more true than for portable, battery-operated applications, where power consumption has perhaps superceded speed and area as the overriding implementation constraint. This adds another degree of freedom - and complexity - to the design process and mandates the need for design techniques and CAD tools that address power, as well as area and speed. This thesis presents a methodology and a set of tools that support low-power system design. Low-power techniques at levels ranging from technology to architecture are presented and their relative merits are compared. Several case studies demonstrate that architecture and system-level optimizations offer the greatest opportunities for power reduction. A survey of existing power analysis tools, however, reveals a marked lack of powerconscious tools at these levels. Addressing this issue, a collection of techniques for modeling power at the register-transfer (RT) level of abstraction is described. These techniques model the impact of design complexity and signal activity on datapath, memory, control, and interconnect power consumption. Several VLSI design examples are used to verify the proposed tools, which exhibit near switch-level accuracy at RTlevel speeds. Finally, an integrated design space exploration environment is described that spans several levels of abstraction and embodies many of the power optimization and analysis strategies presented in this thesis.

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