Abstract not found

Classical logic has so far been the logic of choice in formal hardware verification. This paper proposes the application of intuitionistic logic to the timing analysis of digital circuits. The intuitionistic setting serves two purposes. The model-theoretic properties are exploited to handle the second-order nature of bounded delays in a purely propositional setting without need to introduce explicit time and temporal operators. The proof theoretic properties are exploited to extract quantitative timing information and to reintroduce explicit time in a convenient and systematic way. We present a natural Kripke-style semantics for intuitionistic propositional logic, as a special case of a Kripke constraint model for Propositional Lax Logic [15], in which validity is validity up to stabilisation, and implication oe comes out as "boundedly gives rise to." We show that this semantics is equivalently characterised by a notion of realisability with stabilisation bounds as realisers...

The paper presents a new logical specification language, called Propositional Stabilisation Theory (PST), to capture the stabilisation behaviour of combinational input-output systems. PST is an intuitionistic propositional modal logic interpreted over sets of waveforms. The language is more economic than conventional specification formalisms such as timed Boolean functions, temporal logic, or predicate logic in that it separates function from time and only introduces as much syntax as is necessary to deal with stabilisation behaviour. It is a purely propositional system but has secondorder expressiveness. One and the same Boolean function can be represented in various ways as a PST formula, giving rise to different timing models which associate different stabilisation delays with different parts of the functionality and adjust the granularity of the data-dependency of delays within wide margins. We show how several standard timing analyses can be characterised as algorithms computing c...

Perfectly synchronous systems immediately react to the inputs of their environment, which may lead to so-called causality cycles between actions and their trigger conditions. Algorithms to analyze the consistency of such cycles usually extend data types by an additional value to explicitly indicate unknown values. In particular, Boolean functions are thereby extended to ternary functions. However, a Boolean function usually has several ternary extensions, and the result of the causality analysis depends on the chosen ternary extension. In this paper, we show that there always is a maximal ternary extension that allows one to solve as many causality problems as possible. Moreover, we elaborate the relationship to hazard elimination in hardware circuits, and finally show how the maximal ternary extension of a Boolean function can be efficiently computed by means of binary decision diagrams.

Perfectly synchronous systems immediately react to the inputs of their environment. These instantaneous reactions may result in so-called causality cycles between the actions of a system and their preconditions. Programs with causality cycles may or may not have consistent and unambiguous behaviors. For this reason, compilers have to perform a causality analysis before code generation. In this paper, we analyze the impact of different code generation schemes on causality analysis and propose translations that yield different degrees of causality. To this end, we first translate the program to an equation system as an intermediate representation, which may alternatively be viewed as a hardware circuit. The second step then analyzes the equation system as known from ternary simulation of hardware circuits with combinational feedback loops. In particular, we consider alternative ways to obtain logically equivalent equation systems that show, however, different results in causality analysis.