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Symbolic Reachability Analysis based on SATSolvers
, 2000
"... The introduction of symbolic model checking using Binary Decision Diagrams (BDDs) has led to a substantial extension of the class of systems that can be algorithmically verified. Although BDDs have played a crucial role in this success, they have some wellknown drawbacks, such as requiring an e ..."
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Cited by 86 (3 self)
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The introduction of symbolic model checking using Binary Decision Diagrams (BDDs) has led to a substantial extension of the class of systems that can be algorithmically verified. Although BDDs have played a crucial role in this success, they have some wellknown drawbacks, such as requiring an externally supplied variable ordering and causing space blowups in certain applications. In a parallel development, SATsolving procedures, such as Stalmarck's method or the DavisPutnam procedure, have been used successfully in verifying very large industrial systems. These efforts have recently attracted the attention of the model checking community resulting in the notion of bounded model checking. In this paper, we show how to adapt standard algorithms for symbolic reachability analysis to work with SATsolvers. The key element of our contribution is the combination of an algorithm that removes quantifiers over propositional variables and a simple representation that allows reuse of subformulas. The result will in principle allow many existing BDDbased algorithms to work with SATsolvers. We show that even with our relatively simple techniques it is possible to verify systems that are known to be hard for BDDbased model checkers.
SATbased Verification without State Space Traversal
 In Formal Methods in ComputerAided Design
, 2000
"... . Binary Decision Diagrams (BDDs) have dominated the area of symbolic model checking for the past decade. Recently, the use of satisfiability (SAT) solvers has emerged as an interesting complement to BDDs. SATbased methods are capable of coping with some of the systems that BDDs are unable to h ..."
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Cited by 68 (3 self)
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. Binary Decision Diagrams (BDDs) have dominated the area of symbolic model checking for the past decade. Recently, the use of satisfiability (SAT) solvers has emerged as an interesting complement to BDDs. SATbased methods are capable of coping with some of the systems that BDDs are unable to handle. The most challenging problem that has to be solved in order to adapt standard symbolic model checking to SATsolvers is the boolean quantification necessary for traversing the state space. A possible approach to extending the applicability of SATbased model checkers is therefore to reduce the amount of traversal. In this paper, we investigate a BDDbased verification algorithm due to van Eijk. Van Eijk's algorithm tries to compute information that is sufficient to prove a given safety property directly. When this is not possible, the computed information can be used to reduce the amount of traversal needed by standard model checking algorithms. We convert van Eijk's algori...
Embedded Languages for Describing and Verifying Hardware
, 2001
"... Abstract Lava is a system for designing, specifying, verifying and implementing hardware. It is embedded in the functional programming language Haskell, which means that hardware descriptions are firstclass objects in Haskell. We are thus able to use modern programming language features, such as hi ..."
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Cited by 26 (2 self)
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Abstract Lava is a system for designing, specifying, verifying and implementing hardware. It is embedded in the functional programming language Haskell, which means that hardware descriptions are firstclass objects in Haskell. We are thus able to use modern programming language features, such as higherorder functions, polymorphism, type classes and laziness, in hardware descriptions. We present two rather different versions of Lava. One version realises the embedding by using monads to keep track of the information specified in a hardware description. The other version uses a new language construct, called observable sharing, which eliminates the need for monads so that descriptions are much cleaner. Adding observable sharing to Haskell is a nonconservative extension, meaning that some properties of Haskell are lost. We thus investigate to what extent we are still allowed to use a normal Haskell compiler or interpreter. We also introduce an embedded language for specifying properties. The use of this language is twofold. On the one hand, we can use it to specify and later formally verify properties of the described circuits. On the other hand, we can use it to specify and randomly test properties of normal Haskell programs. As a bonus, since hardware descriptions are embedded in Haskell, we can also use it to test our circuit descriptions.
SATbased methods for sequential hardware equivalence verification without synchronization
 Electronic Notes in Theoretical Computer Science
, 2003
"... The BDD and SATbased model checking and verification methods normally require an initial state. Here we are concerned with sequential hardware verification, where an initial state must be one of the reset states. In practice, a reset state is not always given by the designer, and computing a reset ..."
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Cited by 7 (2 self)
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The BDD and SATbased model checking and verification methods normally require an initial state. Here we are concerned with sequential hardware verification, where an initial state must be one of the reset states. In practice, a reset state is not always given by the designer, and computing a reset state of a circuit is a hard problem. In this paper we propose a method allowing usage of SATbased verification methods without a need for a usergiven or a computed initial state. The idea is to employ a binary encoding of 3valued modeling of circuits, and use the undefined state X as a reset state. 1
Gate Level Description of Synchronous Hardware and Automatic Verification Based on Theorem Proving
, 2001
"... Today's hardware development industry faces enormous problems. The primary reason for this is that the complexity of stateoftheart hardware devices is growing faster than the capacity of the tools that are used to check that they are correct. This problematic situation is further aggravated ..."
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Today's hardware development industry faces enormous problems. The primary reason for this is that the complexity of stateoftheart hardware devices is growing faster than the capacity of the tools that are used to check that they are correct. This problematic situation is further aggravated by an increasing pressure to make the development time as short as possible. As a consequence, components under design are more likely to contain errors, while less time can be spent making sure that finished products are correct. In this thesis, we contribute to improved hardware design methods in two ways. First, we present Lava, a hardware description and verification platform that is embedded in the functional language Haskell. Lava uses the capabilities of the host language to express synchronous circuits in a mathematically precise way, and allows easy connection to external verification tools. Lava also uses the capabilities of Haskell to allow the designer to devise interconnection patterns, and to write parametrised circuit descriptions. We illustrate the power of Lava by describing and verifying hardware components for computing the Fast Fourier Transform (FFT). Second, we present a number of techniques and case studies that demonstrate how automatic theorem proving can be used to prove correctness and find bugs in synchronous hardware. We show how verification can be done both at the level of complex arithmetic, and at the boolean level. In the case of the verification at the arithmetic level, we use Lava to construct special purpose proof strategies that interface with a first order logic theorem prover. In the case of the verification at the boolean level, we convert a number of standard finite state verification methods to use propositional logic theorem provers. ...