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Hardware Design Based on Verilog HDL
, 1998
"... Up to a few years ago, the approaches taken to check whether a hardware component works as expected could be classified under one of two styles: hardware engineers in the industry would tend to exclusively use simulation to (empirically) test their circuits, whereas computer scientists would tend to ..."
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Up to a few years ago, the approaches taken to check whether a hardware component works as expected could be classified under one of two styles: hardware engineers in the industry would tend to exclusively use simulation to (empirically) test their circuits, whereas computer scientists would tend to advocate an approach based almost exclusively on formal verification. This thesis proposes a unified approach to hardware design in which both simulation and formal verification can coexist. Relational Duration Calculus (an extension of Duration Calculus) is developed and used to define the formal semantics of Verilog HDL (a standard industry hardware description language). Relational Duration Calculus is a temporal logic which can deal with certain issues raised by the behaviour of typical hardware description languages and which are hard to describe in a pure temporal logic. These semantics are then used to unify the simulation of Verilog programs, formal verification and the use of algebraic laws during the design stage.
Application Specific Higher Order Logic Theorem Proving
 in Proc. of the Verification Workshop  VERIFY’02, S. Autexier and
, 2002
"... Theorem proving allows the formal verification of the correctness of very large systems. In order to increase the acceptance of theorem proving systems during the design process, we implemented higher order logic proof systems for ANSIC and Verilog within a framework for application specific proo ..."
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Theorem proving allows the formal verification of the correctness of very large systems. In order to increase the acceptance of theorem proving systems during the design process, we implemented higher order logic proof systems for ANSIC and Verilog within a framework for application specific proof systems. Furthermore, we implement the language of the PVS theorem prover as wellestablished higher order specification language. The tool allows the verification of the design languages using a PVS specification and the verification of hardware designs using a C program as specification. We implement powerful decision procedures using Model Checkers and satisfiability checkers. We provide experimental results that compare the performance of our tool with PVS on large industrial scale hardware examples.
Formal Verification of Concurrent Programs Based on Type Theory
, 1998
"... Interactive theorem proving provides a general approach to modeling and verification of both finitestate and infinitestate systems but requires significant human efforts to deal with many tedious proofs. On the other hand, modelchecking is limited to some application domain with small finitestate ..."
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Interactive theorem proving provides a general approach to modeling and verification of both finitestate and infinitestate systems but requires significant human efforts to deal with many tedious proofs. On the other hand, modelchecking is limited to some application domain with small finitestate space. A natural thought for this problem is to integrate these two approaches. To keep the consistency of the integration and ensure the correctness of verification, we suggest to use type theory based theorem provers (e.g. Lego) as the platform for the integration and build a modelchecker to do parts of the verification automatically. We formalise a verification system of both CCS and an imperative language in the proof development system Lego which can be used to verify both finitestate and infinitestate problems. Then a modelchecker, LegoMC, is implemented to generate Lego proof terms for finitestate problems automatically. Therefore people can use Lego to verify a general problem ...
Under consideration for publication in J. Functional Programming 1 Acute: Highlevel programming language design for distributed computation
"... † INRIA Rocquencourt Existing languages provide good support for typeful programming of standalone programs. In a distributed system, however, there may be interaction between multiple instances of many distinct programs, sharing some (but not necessarily all) of their module structure, and with som ..."
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† INRIA Rocquencourt Existing languages provide good support for typeful programming of standalone programs. In a distributed system, however, there may be interaction between multiple instances of many distinct programs, sharing some (but not necessarily all) of their module structure, and with some instances rebuilt with new versions of certain modules as time goes on. In this paper we discuss programminglanguage support for such systems, focussing on their typing and naming issues. We describe an experimental language, Acute, which extends an ML core to support distributed development, deployment, and execution, allowing typesafe interaction between separatelybuilt programs. The main features are: (1) typesafe marshalling of arbitrary values; (2) type names that are generated (freshly and by hashing) to ensure that type equality tests suffice to protect the invariants of abstract types, across the entire distributed system; (3) expressionlevel names generated to ensure that name equality tests suffice for type safety of associated values, e.g. values carried on named channels; (4) controlled dynamic rebinding of marshalled values to local resources; and (5) thunkification of threads and mutexes to support computation mobility.