This paper describes the design and performance of IDES, a Java-based distributed simulation engine being developed at Sandia National Laboratories. The feasability of using Java is demonstrated by achieving order of magnitude speedup gains, on a model with three quarters of a million simulated entities, on a "off-the-shelf " system of 56 PentiumPro processors. 1. Introduction The Infrastructure for Distributed Enterprise Simulation (IDES), is a distributed simulation engine under development at the Sandia National Laboratories. As one of IDES's principle goals was portability and use in heterogeneous computing environments, we have implemented IDES in Java. This paper describes IDES's organization, and reports on overhead costs of executing simulations under IDES, on a large-scale computing system built of clusters of PentiumPro processors. While overall processing rates are fully in accordance with Java's reputation for slowness, we find that by increasing the number of processors ...

In the past decade, parallel processing has gained very significant advances in all fronts of the theory, systems, and applications. However, despite years of research and its apparent significance, parallel simulation remains a major outstanding challenge. In particular, there has been no simulation system which facilitates an early prediction of the program performance. In this report, we document a survey of the major existing approaches for parallel simulation as well as a comparative study of two leading computational models, namely, Valiant's BSP and Leiserson's Cilk, which are useful formal models for performance prediction of simulation programs. 1 Introduction Simulation has been heavily relied upon by computer scientists, physicists, circuit designers, mathematicians, military force, and even video game designers [LK91, Fis95, Chi92]. For decades, simulationists have been devising simulation models for large and complex systems to facilitate performance analysis, stud...

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The development of efficient parallel discrete event simulators is hampered by the large number of interrelated factors affecting performance. This problem is made more difficult by the lack of scalable representative models that can be used to analyze optimizations and isolate bottlenecks. This paper proposes a performance and scalabilty analysis framework (PSAF) for parallel discrete event simulators. PSAF is built on a platform-independent workload specification language (WSL). WSL is a language that represents simulation models using a set of fundamental performance-critical parameters. For each simulator under study, a WSL translator generates synthetic platform-specific simulation models that conform to the performance and scalability characteristics specified by the WSL description. Moreover, sets of portable simulation models that explore the effects of the different parameters, individually or collectively, on the execution performance can easily be constructed using the synthetic workload generator (SWG). The SWG automatically generates simulation workloads with different performance properties. In addition, PSAF supports the seamless integration of real simulation models into the workload specification. Thus, a benchmark with both real and synthetically generated models can be built allowing for realistic and thorough exploration of the performance space. The utility of PSAF in determining the boundaries of performance and scalability of simulation environments and models is demonstrated.

Parallel discrete event simulation (PDES) is efficient in simulating a large digital circuit. In this dissertation, two techniques are proposed to improve the performance of PDES in logic simulation. One is a partitioning algorithm and the other is a hybrid parallel simulation protocol. Experiments were performed to demonstrate that the two proposed techniques together provide significant reduction in parallel simulation time. Unlike most other partitioning algorithms, the proposed partitioning algorithm preserves circuit concurrency by assigning circuit gates that can be evaluated at about the same time to different processors. As a result, the concurrency preserving partitioning (CPP) algorithm can provide instantaneous load balancing, instead of only aggregated load balancing, throughout the period of a parallel simulation. This is especially important when the algorithm is used together with a Time Warp simulation where a high degree of concurrency can lead to fewer rollbacks and better performance. In addition, a new concurrency metric is proposed to evaluate partitioning algorithms before the execution of parallel simulations. Even though PDES can reduce the logic simulation time for large circuits considerably, it generates more events than necessary for certain high activity circuits and produces inconsistent speedup over different circuits. The proposed Event Lookahead Time Warp (ETW) algorithm can look ahead and combine and execute multiple events at each gate optimistically so that the probability of unnecessary events can be reduced. As a result, it can reduce rollback cost, obtain better load balance, and achieve more consistent execution times and reasonable speedups.

Final approval and acceptance of this dissertation is contingent upon the candidate’s submission of the final copies of the dissertation to the Graduate College. I hereby certify that I have read this dissertation prepared under my direction and recommend that it be accepted as fulfilling the dissertation requirement.

Many Time Warp simulation tools are used by a wide variety of application developers, each with different demands and patterns of use. It is unlikely, under these circumstances, for off-the-shelf simulation software to be "optimal" for any application in any processing environment. The main form of adaptation that is presently available is hand-crafted and problem specific; where the needs and patterns of use of the application are defined and the Time Warp simulation kernel software is fitted to optimize the performance of this typical application. The problem with this is, by their nature, Time Warp simulations are subject to constant change and adaptation. This situation is exacerbated by changes in network topology and hardware platforms. For most simulations, successfully adapting to the imbalances in the system is often a question of dynamically adjusting the right set of parameters in the executing simulation. Unfortunately, due to the dynamic nature of Time Warp simulation systems, identification of this critical set of parameters is not trivial. Also, modifying these parameters in the simulation system affects both the executing simulation and the execution environment. Hence, in addition to studying methods to adjust the set of critical parameters, the effect of these adjustments on the execution and the system resources must also be investigated.

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Cellular space modeling is becoming an increasingly important modeling paradigm for modeling complex systems with spatial-temporal behaviors. The growing demand for cellular space models has directed researchers to use different modeling formalisms, among which Discrete Event System Specification (DEVS) is widely used due to its formal modeling and simulation framework. The increasing complexity of systems to be modeled asks for cellular space models with large number of cells for modeling the systems ’ spatial-temporal behavior. Improving simulation performance becomes crucial for simulating large scale cellular space models. In this dissertation, we proposed a framework for improving simulation performance for large scale DEVS-based cellular space models. The framework has a layered structure, which includes modeling, simulation, and network layers corresponding to the DEVS-based modeling and simulation architecture. Based on this framework, we developed methods at each layer to overcome performance issues for simulating large scale cellular space models. Specifically, toincrease the runtime and memory efficiency for simulating large number of cells, we applied Dynamic Structure DEVS (DSDEVS) to cellular space modeling and carried out comprehensive

Abstract-- Dynamic Structure DEVS (DSDEVS) is an advanced modeling formalism that allows DEVS models and their couplings to be dynamically changed. The modeling power and advantages of DSDEVS have been well studied. However, the performance aspect of DSDEVS is generally overlooked. This paper provides a comprehensive performance measurement of DSDEVS for a large scale cellular space models. We consider both the modeling layer and simulation layer for performance analysis, and carry out performance measurement based on a token ring model and a fire spread model. The results shows that DS modeling can improve simulation performance for large scale cellular space models, due to the fact that it makes the simulation focus only on those active models, and thus be more efficient than when the entire cellular space is loaded. On the other hand, the DS overhead cannot be ignored and can become significant and even dominant when large number of cells are dynamically added/deleted.