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The Semantic Challenge of Verilog HDL
 IN TENTH ANNUAL IEEE SYMPOSIUM ON LOGIC IN COMPUTER SCIENCE, IEEE COMPUTER
, 1995
"... The Verilog hardware description language (HDL) is widely used to model the structure and behaviour of digital systems ranging from simple hardware building blocks to complete systems. Its semantics is based on the scheduling of events and the propagation of changes. Different Verilog models of the ..."
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Cited by 34 (1 self)
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The Verilog hardware description language (HDL) is widely used to model the structure and behaviour of digital systems ranging from simple hardware building blocks to complete systems. Its semantics is based on the scheduling of events and the propagation of changes. Different Verilog models of the same device are used during the design process and it is important that these be `equivalent'; formal methods for ensuring this could be commercially significant. Unfortunately, there is very little theory available to help. This selfcontained tutorial paper explains the semantics of Verilog informally and poses a number of logical and semantic problems that are intended to provoke further research. Any theory developed to support Verilog is likely to be useful for the analysis of the similar (but more complex) language VHDL.
Formal Reasoning with Verilog HDL
 In Workshop on Formal Techniques for Hardware and Hardwarelike Systems, Marstrand
, 1998
"... Most hardware verification techniques tend to fall under one of two broad, yet separate caps: simulation or formal verification. This paper briefly presents a framework in which formal verification plays a crucial role within the standard approach currently used by the hardware industry. As a basis ..."
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Cited by 8 (2 self)
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Most hardware verification techniques tend to fall under one of two broad, yet separate caps: simulation or formal verification. This paper briefly presents a framework in which formal verification plays a crucial role within the standard approach currently used by the hardware industry. As a basis for this, the formal semantics of Verilog HDL are defined, and properties about synchronization and mutual exclusion algorithms are proved.
A Model of VHDL for the Analysis, Transformation, and Optimization of Digital System Designs
 In Conference on Hardware Description Languages (CHDL '95
, 1995
"... Besides a formal syntax definition, few formal semantic models for HDLs are ever constructed. This paper reports our efforts to construct formal models for the hardware description language VHDL. In particular, a static model for VHDL that addresses wellformedness, static equivalences, and static r ..."
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Cited by 3 (2 self)
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Besides a formal syntax definition, few formal semantic models for HDLs are ever constructed. This paper reports our efforts to construct formal models for the hardware description language VHDL. In particular, a static model for VHDL that addresses wellformedness, static equivalences, and static rewriting is presented. A rewriting algebra is presented that defines a set of transforms that allow the rewriting of VHDL descriptions into a reduced form. The dynamic semantics is under development and the reductions attained by the rewriting algebra have greatly simplified the language constructs that the dynamic semantics have to characterize. I. Introduction Hardware Description Languages (HDLs) and their affiliated design tools are widely used to aid the computer architect in the design and implementation of digital systems. In many cases such languages and tools are proprietary systems  used locally at only one or two sites. However, advances in design automation have driven the co...
An Overview of the Formal Specification and Verification of the FM9001 Microprocessor
, 1994
"... This document presents the details of the FM9001 development, its specification, and its verification. 1 RESULTS ..."
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Cited by 3 (0 self)
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This document presents the details of the FM9001 development, its specification, and its verification. 1 RESULTS
Distinguishing Formulas for Free
 in Proc. EDACâ€“EUROASICâ€™93: IEEE European Design Automation Conference
, 1993
"... A system for the efficient verification of the input/output correctness of Finite State Machines with data path and control unit is presented. This system, which is based on FirstOrder Logic theorem proving, is unique in automatically providing distinguishing formulas expressing all test patterns th ..."
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Cited by 2 (0 self)
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A system for the efficient verification of the input/output correctness of Finite State Machines with data path and control unit is presented. This system, which is based on FirstOrder Logic theorem proving, is unique in automatically providing distinguishing formulas expressing all test patterns that witness a behavioural difference between two descriptions. Experimental results illustrate the test pattern generation feature for stuckat faults, functional faults, and initialization faults, and the efficiency which results from the compositionality of the verification. Keywords: High Level Design Tools  design verification. This work has been supported by the Graduiertenkolleg at the RWTH Aachen, Germany. 1 Introduction Traditional symbolic verification methods for Finite State Machines of the complexity of a microprocessor either separately address the data path and the control unit (eg. [CMPr91, NKFT90, Vemu89]), or only reduced subsets of Register Transfer level languages [Fi...
A Formal Language for the Specification and Verification of. . .
, 1993
"... ruct (mod trigger d) (list 'sequential (inputs mod) (collectoutputs mod d) (collectmodes mod) (collectdelays mod d) trigger (collectlocals mod) (collectstate mod d) (minimumperiod mod d) (collectsetups mod d) (collectholds mod d))) ()) (if (member out (inputs mod)) f (if (sequentialp (find ..."
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ruct (mod trigger d) (list 'sequential (inputs mod) (collectoutputs mod d) (collectmodes mod) (collectdelays mod d) trigger (collectlocals mod) (collectstate mod d) (minimumperiod mod d) (collectsetups mod d) (collectholds mod d))) ()) (if (member out (inputs mod)) f (if (sequentialp (findsubmodule out mod)) t (if (zerop d) f (checkoutputs$ 'list (findinputs out mod) mod (sub1 d)))))) ((ordlessp (lex (list d (count out)))))) (defn checkseqstruct (mod trigger d) (and (checkoutputs$ 'list (outputs mod) mod d) (checkinternal mod (submodules mod) (subinputs mod) (suboutputs mod) (car (inputs mod)) trigger d))) ;;The minimum clock period is bounded by the maximum of the periods of ;;the sequential components. It also must be long enough to allow ;;internal signals to stabilize in order to respect setup times: (defn minimumperiod$ (submods subouts mod d) (if (listp submods) (if (sequentialp (car submods)) (max (max (period (car submods)) (fmaxl (addmaxdelays
A Model for the Dynamic Semantics of VHDL for CAD Tool Optimization
, 1995
"... Present day hardware complexity mandates prior simulation of designs to achieve some level of confidence about their correctness. The hardware description language VHDL is widely used to describe and simulate hardware designs. However, the semantics of VHDL, presented in informal prose form in the L ..."
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Present day hardware complexity mandates prior simulation of designs to achieve some level of confidence about their correctness. The hardware description language VHDL is widely used to describe and simulate hardware designs. However, the semantics of VHDL, presented in informal prose form in the Language Reference Manual (LRM), is ambiguous and therefore needs to be formalized. Past efforts in characterizing VHDL are lacking in either that they handle only a small subset of VHDL or that they simply describe the simulation cycle as prescribed by the LRM (usually both). In this work, a comprehensive, declarative semantics for VHDL is presented which is independent of the simulation cycle and uses a temporal logic that captures the timing constraints crucial to the understanding of a discrete event based language like VHDL. The semantics is presented as a construction of sets of time intervals over which the values of signals, ports and variables are defined. It is argued that this sema...
(reducestructure (list 'structural
"... namedstruct (mod trigger d) (list 'sequential (inputs mod) (collectoutputs mod d) (collectmodes mod) (collectdelays mod d) trigger (collectlocals mod) (collectstate mod d) (minimumperiod mod d) (collectsetups mod d) (collectholds mod d))) 85 ()) (if (member out (inputs mod)) f (if (sequent ..."
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namedstruct (mod trigger d) (list 'sequential (inputs mod) (collectoutputs mod d) (collectmodes mod) (collectdelays mod d) trigger (collectlocals mod) (collectstate mod d) (minimumperiod mod d) (collectsetups mod d) (collectholds mod d))) 85 ()) (if (member out (inputs mod)) f (if (sequentialp (findsubmodule out mod)) t (if (zerop d) f (checkoutputs$ 'list (findinputs out mod) mod (sub1 d)))))) ((ordlessp (lex (list d (count out)))))) (defn checkseqstruct (mod trigger d) (and (checkoutputs$ 'list (outputs mod) mod d) (checkinternal mod (submodules mod) (subinputs mod) (suboutputs mod) (car (inputs mod)) trigger d))) ;;The minimum clock period is bounded by the maximum of the periods of ;;the sequential components. It also must be long enough to allow ;;internal signals to stabilize in order to respect setup times: (defn minimumperiod$ (submods subouts mod d) (if (listp submods) (if (sequentialp (car submods)) (max (max (period (car submods)) (fmaxl (a