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An Operational Semantics of a Simulator Algorithm
 International Institute for Software Technology, United Nations University
, 2000
"... The semantics of a hardware description language is usually given informally in terms of how a simulator should behave. We give an operational semantics of simple version of Verilog hardware description language. We also outline some techniques of possible formal reasoning based on the operational s ..."
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Cited by 11 (3 self)
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The semantics of a hardware description language is usually given informally in terms of how a simulator should behave. We give an operational semantics of simple version of Verilog hardware description language. We also outline some techniques of possible formal reasoning based on the operational semantics.
Towards a Formal Semantics of Verilog using Duration Calculus
 Formal Techniques for RealTime and Fault Tolerant Systems (FTRTFT'98). LNCS
, 1998
"... We formalise the semantics of V \Gamma , a simple version of Verilog hardware description language using an extension of Duration Calculus. The language is simple enough for experimenting formalisation, but contains sufficient features for being practically relevant. V \Gamma programs can exhibi ..."
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We formalise the semantics of V \Gamma , a simple version of Verilog hardware description language using an extension of Duration Calculus. The language is simple enough for experimenting formalisation, but contains sufficient features for being practically relevant. V \Gamma programs can exhibit a rich variety of computations, and it is therefore necessary to extend Duration Calculus with several features, including Weakly Monotonic Time, infinite intervals and fixed point operators. The semantics is compositional and can be used as the formal basis of a formal theory of Verilog. Gerardo Schneider is a fellow of UNU/IIST, on leave from Catholic University of Pelotas, Brazil, where he is a lecturer. Xu Qiwen is a Research Fellow of UNU/IIST. His research interest is in Formal Techniques of Programming, including Theory for Concurrency and Real Time, Verification and Design Calculi. Email: qxu@iist.unu.edu Copyright c fl 1998 by UNU/IIST, Gerardo Schneider and Xu Qiwen Contents...
A Formal Executable Semantics of Verilog
"... This paper describes a formal executable semantics for the Verilog hardware description language. The goal of our formalization is to provide a concise and mathematically rigorous reference augmenting the prose of the official language standard, and ultimately to aid developers of Verilogbased tools ..."
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Cited by 7 (1 self)
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This paper describes a formal executable semantics for the Verilog hardware description language. The goal of our formalization is to provide a concise and mathematically rigorous reference augmenting the prose of the official language standard, and ultimately to aid developers of Verilogbased tools; e.g., simulators, test generators, and verification tools. Our semantics applies equally well to both synthesizeable and behavioral designs and is given in a familiar, operationalstyle within a logic providing important additional benefits above and beyond static formalization. In particular, it is executable and searchable so that one can ask questions about how a, possibly nondeterministic, Verilog program can legally behave under the formalization. The formalization should not be seen as the final word on Verilog, but rather as a starting point and basis for community discussions on the Verilog semantics.
Towards an Operational Semantics of Verilog
, 1998
"... We give an operational semantics of simple version of Verilog hardware description language. Gerardo Schneider is a fellow of UNU/IIST, on leave from Catholic University of Pelotas, Brazil, where he is a lecturer. Xu Qiwen is a Research Fellow of UNU/IIST. His research interest is in Formal Techniq ..."
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Cited by 6 (0 self)
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We give an operational semantics of simple version of Verilog hardware description language. Gerardo Schneider is a fellow of UNU/IIST, on leave from Catholic University of Pelotas, Brazil, where he is a lecturer. Xu Qiwen is a Research Fellow of UNU/IIST. His research interest is in Formal Techniques of Programming, including Theory for Concurrency and Real Time, Verification and Design Calculi. Email: qxu@iist.unu.edu Copyright c fl 1998 by UNU/IIST, Gerardo Schneider and Xu Qiwen Contents i Contents 1 Introduction 1 2 A Subset of Verilog and its Operational Semantics 1 2.1 Procedural Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.2 Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.3 Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.4 Event control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.5 Continuous Assignment . . ....
Putting Operational Techniques to the Test: A Syntactic Theory for Behavioral Verilog
"... We present a syntactic theory for the behavioral subset of the Verilog Hardware Description Language. Due to the complexity of the language, the construction of this theory represents a serious test of the suitability of syntactic operational techniques for reasoning about industrial languages. Over ..."
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We present a syntactic theory for the behavioral subset of the Verilog Hardware Description Language. Due to the complexity of the language, the construction of this theory represents a serious test of the suitability of syntactic operational techniques for reasoning about industrial languages. Overall, we have found that these techniques are rather robust but with a few caveats. Our theory formalizes the simulation cycle explicitly, exposes a number of ambiguities and inconsistencies in the language reference manual (LRM), and is the most accurate known description of this subset of Verilog, with respect to the LRM. The syntactic theory has been used to automatically derive a simulator for Verilog. 1 Introduction Programming calculi, which concentrate on a small set of constructs that capture the "essence" of a language, commonly come equipped with syntactic theories that explain, in intuitive yet formal terms, the evaluation and optimization of programs. In principle, then, the deve...
A formal description of behavioral Verilog based on axiomatic semantics
, 1998
"... My thanks first of all to my advisor, Dr.Amr Sabry. Without his exceptional inspiration and guidance, as well as the occasional kick in the pants (much needed), this project would not exist. Thanks to Steven Sharp and Steve Meyer for their helpful correspondences and explanation of Verilog semantics ..."
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My thanks first of all to my advisor, Dr.Amr Sabry. Without his exceptional inspiration and guidance, as well as the occasional kick in the pants (much needed), this project would not exist. Thanks to Steven Sharp and Steve Meyer for their helpful correspondences and explanation of Verilog semantics. And thanks to the members of the Internet Verilog community of comp.lang.verilog who participated in my nonblocking assignment experiment—Hitesh Brahmbhatt, Larice Robert, Magnus Soderberg, Edward Arthur, and Robert Szczygiel. Thank you to Daryl Stewart for reading this work, and for finding two small (but important) bugs. Finally, a huge thank you to Janet, my life partner and closest friend—for being there. Dedication To my parents, who taught me to look, Bob Horn, who taught me how, and to Janet, who helped me to know what I saw.
A Calculus of Signals
, 2000
"... An elementary theory is proposed for reasoning about circuits at the timed level. Its relationship to traditional differential calculus is explored; it is applied to the analysis of circuits with feedback; and algorithms for detection of transients and hazards are given. Finally a small case study, ..."
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An elementary theory is proposed for reasoning about circuits at the timed level. Its relationship to traditional differential calculus is explored; it is applied to the analysis of circuits with feedback; and algorithms for detection of transients and hazards are given. Finally a small case study, of a positiveedgetriggered register, is presented. Emphasis is on the use of laws which draw on the intuition gained from traditional dierential calculus. Key words: formal methods; signal; hazard analysis; timing. 1
Correct Hardware Compilation with Verilog HDL
"... . Hardware description languages usually include features which do not have a direct hardware interpretation. Recently, synthesis algorithms allowing some of these features to be compiled into circuits have been developed and implemented. Using a formal semantics of Verilog based on Relational Durat ..."
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. Hardware description languages usually include features which do not have a direct hardware interpretation. Recently, synthesis algorithms allowing some of these features to be compiled into circuits have been developed and implemented. Using a formal semantics of Verilog based on Relational Duration Calculus, we give a number of algebraic laws which Verilog programs obey, using which, we then prove the correctness of a hardware compilation procedure. 1