This paper presents a technique for preprocessing combinational logic before technology mapping. The technique is based on the representation of combinational logic using And-Inverter Graphs (AIGs), the networks of two-input ANDs and inverters. The optimization works by alternating DAG-aware AIG rewriting, which reduces area by sharing common logic without increasing delay, and algebraic AIG balancing, which minimizes delay without increasing area. The new technology-independent flow is implemented in a public-domain tool ABC. Experiments on large industrial benchmarks show that the proposed methodology scales to very large designs and is several orders of magnitude faster than SIS and MVSIS while offering comparable or better quality when measured by the quality of the network after mapping. 1

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This paper presents an algorithm for a non-standard logicminimization problem that arises in 3-valued propositional logic. The problem is motivated by the potential for obtaining better answers in applications that use 3-valued logic. An answer of 0 or 1 provides precise (definite) information; an answer of 1=2 provides imprecise (indefinite) information. By replacing a formula ' with a "better" formula , we may improve the precision of the answers obtained. In this paper, we give an algorithm that always produces a formula that is "best" (in a certain well-defined sense).

A transformation of multi-valued input binary-output functions, called co-singleton transform (CST), was introduced in [11] to reduce algebraic multi-valued (MV) operations to binary. In this paper, we explore its potential for a number of problems related to MV SOP minimization, such as computing ISOPs, the set of all primes, and the set of all essential primes. Experimental results show that in some cases these problems can be solved more efficiently than by the traditional MV SOP minimization approaches represented by ESPRESSO-MV, but that generally there is no clear method-of-choice. 1

We present an algorithm that restructures the state transition graph (STG) of a sequential circuit so as to reduce power dissipation. The STG is modified without changing the behavior of the circuit, by exploiting state equivalence. Rather than aiming primarily at reducing the number of states, our algorithm redirects transitions so that the new destination states are equivalent to the original ones, while the average activity of the circuit is decreased. The impact on area is also estimated to increase the accuracy of the power analysis. The STG and all other major data structures are stored as decision diagrams, and the algorithm does not enumerate explicitly the states or the transitions. (i.e., it is symbolic.) Therefore, it can deal with circuits that have millions of states. Once the STG has been restructured we apply symbolic factoring algorithms, based on Zero-suppressed BDDs, to convert the optimized graph into a multilevel circuit. We derive an efficient circuit from the BDDs...

This thesis investigates practical and theoretical concerns for the use of Binary Decision Diagrams (BDDs) for qualitative and quantitative risk assessments of complex systems. Boolean models describing failure relationships between components, and fault trees in particular, are boolean formulas whose variables are individual component failures; assessment of these models can be performed by analysis of the boolean function induced by the formula. Resource consumption for BDD computations, which is determined by the form of the boolean formula and the order imposed on its variables, is in many cases exponentially smaller than the truth table for the function. The use of Binary Decision Diagrams has made possible orders-of-magnitude increases in the complexity of systems that can be assessed efficiently. Nonetheless, the practical limits of straightforward use of BDDs for reliability analysis are often surpassed by real-world systems. Understanding why this happens is the first subject...

We propose a new way of decomposing completely or incompletely specified Boolean functions into a set of unate functional blocks to obtain a good initial structure for logic synthesis. The input to our algorithm is a flattened netlist. The output is a multi-level netlist that can be efficiently implemented using a logic synthesis tool. Experimental results on Espresso PLA benchmarks employing a state of the art commercial synthesis tool show that our technique leads to an average 11 % improvement in the area after technology mapping, without sacrificing on speed. 1

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