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Optimizing dominant time constant in RC circuits
, 1996
"... We propose to use the dominant time constant of a resistorcapacitor (RC) circuit as a measure of the signal propagation delay through the circuit. We show that the dominant time constant is a quasiconvex function of the conductances and capacitances, and use this property to cast several interestin ..."
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Cited by 15 (7 self)
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We propose to use the dominant time constant of a resistorcapacitor (RC) circuit as a measure of the signal propagation delay through the circuit. We show that the dominant time constant is a quasiconvex function of the conductances and capacitances, and use this property to cast several interesting design problems as convex optimization problems, specifically, semidefinite programs (SDPs). For example, assuming that the conductances and capacitances are affine functions of the design parameters (which is a common model in transistor or interconnect wire sizing), one can minimize the power consumption or the area subject to an upper bound on the dominant time constant, or compute the optimal tradeoff surface between power, dominant time constant, and area. We will also note that, to a certain extent, convex optimization can be used to design the topology of the interconnect wires. This approach has two advantages over methods based on Elmore delay optimization. First, it handles a far wider class of circuits, e.g., those with nongrounded capacitors. Second, it always results in convex optimization problems for which very efficient interiorpoint methods have recently been developed. We illustrate the method, and extensions, with several examples involving optimal wire and transistor sizing.
A General Approach to Performance Analysis and Optimization of Asynchronous Circuits
, 1995
"... A systematic approach for evaluating and optimizing the performance of asynchronous VLSI circuits is presented. Indexpriority simulation is introduced to efficiently find minimal cycles in the state graph of a given circuit. These minimal cycles are used to determine the causality relationships bet ..."
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Cited by 14 (0 self)
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A systematic approach for evaluating and optimizing the performance of asynchronous VLSI circuits is presented. Indexpriority simulation is introduced to efficiently find minimal cycles in the state graph of a given circuit. These minimal cycles are used to determine the causality relationships between all signal transitions in the circuit. Once these relationships are known, the circuit is then modeled as an extended eventrule system, which can be used to describe many circuits, including ones that are inherently disjunctive. An accurate indication of the performance of the circuit is obtained by analytically computing the period of the corresponding extended eventrule system.
Speeding up Pipelined Circuits through a Combination of Gate Sizing and Clock Skew Optimization
 Proc. Int'l Conf. on ComputerAided Design
, 1995
"... An algorithm for unifying the techniques of gate sizing and clockskew optimization for acyclic pipelines is presented in this paper. In the design of circuits under very tight timing specifications, the area overhead of gate sizing can be considerable. The procedure utilizes the idea of cycleborrow ..."
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Cited by 12 (0 self)
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An algorithm for unifying the techniques of gate sizing and clockskew optimization for acyclic pipelines is presented in this paper. In the design of circuits under very tight timing specifications, the area overhead of gate sizing can be considerable. The procedure utilizes the idea of cycleborrowing using clock skew optimization to relax the stringency of the timing specification on the critical stages of the pipeline. Experimental results verify that cycleborrowing using sizing+skew results in a better overall areadelay tradeoff than with sizing alone.
A Transistor Reordering Algorithm for the Performance Optimization of CMOS Digital Circuits
, 1992
"... Abstract A model which estimates the relative difference between the best and worst propagation delays of a CMOS complex gate with respect to the order of its transistors, and an algorithm which performs transistor reordering based on this model to significantly reduce propagation delays are presen ..."
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Abstract A model which estimates the relative difference between the best and worst propagation delays of a CMOS complex gate with respect to the order of its transistors, and an algorithm which performs transistor reordering based on this model to significantly reduce propagation delays are presented. Since the algorithm presented in this paper uses a general circuit model based on the results of SPICE simulations, it can be used for circuits of arbitrary functionality and size. Furthermore, it can be used in any semicustom design environment (e.g., gate array, standard cell), since it is not dependent on a cell library. Although the model is process dependent, it can be parameterized for a new fabrication process automatically. Experimental results for the circuits tested thus far show that the improvement in propagation delay can be as much as 22 percent.. I
Timing Optimization By Gate Resizing And Critical Path Identification
 IEEE trans. On CAD of Integrated Circuits and Systems
, 1995
"... Due to the rapid progress in VLSI technology, the overall complexity of the chip has increased dramatically. There is a simultaneous need for more functions and higher speed in modern VLSI engineering. Therefore, using a minimum amount of extra hardware to meet timing requirements is becoming a majo ..."
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Due to the rapid progress in VLSI technology, the overall complexity of the chip has increased dramatically. There is a simultaneous need for more functions and higher speed in modern VLSI engineering. Therefore, using a minimum amount of extra hardware to meet timing requirements is becoming a major issue in VLSI design. Here, we propose an efficient method for timing optimization using gate resizing. To control the hardware overhead, a minimum (or as small as possible) number of gates are selected for resizing with the aid of a powerful benefit function. To guarantee the performance of timing optimization, a modified version of PODEM [1], called PODEM, ensures that each resized gate is located on at least one critical path. Thus, resizing a gate definitely reduces circuit delay. Simulation results demonstrate that our timing optimization method can efficiently reduce circuit delay with a limited amount of gate resizing. 1 1. Introduction In recent years, semiconductor technology h...