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Checkpointing and its applications
 IEEE, IEEE Computer Society
, 1995
"... Is the Framingham coronary heart disease absolute risk function ..."
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Cited by 106 (8 self)
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Is the Framingham coronary heart disease absolute risk function
Optimizing dominant time constant in RC circuits
, 1996
"... We propose to use the dominant time constant of a resistorcapacitor (RC) circuit as a measure of the signal propagation delay through the circuit. We show that the dominant time constant is a quasiconvex function of the conductances and capacitances, and use this property to cast several interestin ..."
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Cited by 15 (7 self)
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We propose to use the dominant time constant of a resistorcapacitor (RC) circuit as a measure of the signal propagation delay through the circuit. We show that the dominant time constant is a quasiconvex function of the conductances and capacitances, and use this property to cast several interesting design problems as convex optimization problems, specifically, semidefinite programs (SDPs). For example, assuming that the conductances and capacitances are affine functions of the design parameters (which is a common model in transistor or interconnect wire sizing), one can minimize the power consumption or the area subject to an upper bound on the dominant time constant, or compute the optimal tradeoff surface between power, dominant time constant, and area. We will also note that, to a certain extent, convex optimization can be used to design the topology of the interconnect wires. This approach has two advantages over methods based on Elmore delay optimization. First, it handles a far wider class of circuits, e.g., those with nongrounded capacitors. Second, it always results in convex optimization problems for which very efficient interiorpoint methods have recently been developed. We illustrate the method, and extensions, with several examples involving optimal wire and transistor sizing.
Application of Layout Matrices to the Design of CMOS Functional Cells
, 2000
"... this paper formalises the way in which a schematic of a static CMOS gate is converted into an optimised mask layout. The basic design steps consists of: ..."
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this paper formalises the way in which a schematic of a static CMOS gate is converted into an optimised mask layout. The basic design steps consists of:
Eye: A Tool For Measuring The Defect Sensitivity Of Ic Layout
"... This paper addresses the problem of design for manufacture of IC layout by presenting a tool that enables the measurement of critical area [1] and hence layout defect sensitivity. ..."
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This paper addresses the problem of design for manufacture of IC layout by presenting a tool that enables the measurement of critical area [1] and hence layout defect sensitivity.