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Optimizing dominant time constant in RC circuits
, 1996
"... We propose to use the dominant time constant of a resistorcapacitor (RC) circuit as a measure of the signal propagation delay through the circuit. We show that the dominant time constant is a quasiconvex function of the conductances and capacitances, and use this property to cast several interestin ..."
Abstract

Cited by 16 (7 self)
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We propose to use the dominant time constant of a resistorcapacitor (RC) circuit as a measure of the signal propagation delay through the circuit. We show that the dominant time constant is a quasiconvex function of the conductances and capacitances, and use this property to cast several interesting design problems as convex optimization problems, specifically, semidefinite programs (SDPs). For example, assuming that the conductances and capacitances are affine functions of the design parameters (which is a common model in transistor or interconnect wire sizing), one can minimize the power consumption or the area subject to an upper bound on the dominant time constant, or compute the optimal tradeoff surface between power, dominant time constant, and area. We will also note that, to a certain extent, convex optimization can be used to design the topology of the interconnect wires. This approach has two advantages over methods based on Elmore delay optimization. First, it handles a far wider class of circuits, e.g., those with nongrounded capacitors. Second, it always results in convex optimization problems for which very efficient interiorpoint methods have recently been developed. We illustrate the method, and extensions, with several examples involving optimal wire and transistor sizing.
The role of velocity saturation in the switching delay of an RC loaded inverter
, 1994
"... Abstract. Exact analytical expressions for the switching delay of an inverter driving an RC load, taking into account the velocity saturation, are obtained. Modified expressions to include theeffectofsource resistance arethen presented.Owing to the limitation on switching current imposed by the velo ..."
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Abstract. Exact analytical expressions for the switching delay of an inverter driving an RC load, taking into account the velocity saturation, are obtained. Modified expressions to include theeffectofsource resistance arethen presented.Owing to the limitation on switching current imposed by the velocity saturation mechanism, the switching delay is substantially increased for identical widthiolength ratios of the MOSFET in a complementary MOS logic circuit. Obviously, it is important to increase the saturation velocity by miniband engineering or otherwise to improve the performance. However, it is found that the improvements in the time delay are marginal after a saturation velocity of 2.4 x lO'cm s ' is reached. The effect of technologies aimed at circumventing the hotelectron and other deleterious effects is a longer delay time of the circuit due to increased series resistance. However, the effect of increased series resistance is substantially damped due to velocity safuration. These results are particularly important in designing CMOS circuits with submicrometre MOSFET dimensions 1.
HIGHLIGHTS IN PHYSICAL SIMULATION AND ANALYSIS AT ICCAD
"... Six papers were chosen to represent twenty years of research in physical simulation and analysis, three papers addressing the problem of extracting and simulating interconnect effects and three papers describing techniques for simulating steadystate and noise behavior in RF circuits. In this commen ..."
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Six papers were chosen to represent twenty years of research in physical simulation and analysis, three papers addressing the problem of extracting and simulating interconnect effects and three papers describing techniques for simulating steadystate and noise behavior in RF circuits. In this commentary paper we will try to describe the contribution of each paper and place that contribution in some historical context.