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16
Digital Circuit Optimization via Geometric Programming
 Operations Research
, 2005
"... informs ® doi 10.1287/opre.1050.0254 © 2005 INFORMS This paper concerns a method for digital circuit optimization based on formulating the problem as a geometric program (GP) or generalized geometric program (GGP), which can be transformed to a convex optimization problem and then very efficiently s ..."
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Cited by 27 (7 self)
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informs ® doi 10.1287/opre.1050.0254 © 2005 INFORMS This paper concerns a method for digital circuit optimization based on formulating the problem as a geometric program (GP) or generalized geometric program (GGP), which can be transformed to a convex optimization problem and then very efficiently solved. We start with a basic gate scaling problem, with delay modeled as a simple resistorcapacitor (RC) time constant, and then add various layers of complexity and modeling accuracy, such as accounting for differing signal fall and rise times, and the effects of signal transition times. We then consider more complex formulations such as robust design over corners, multimode design, statistical design, and problems in which threshold and power supply voltage are also variables to be chosen. Finally, we look at the detailed design of gates and interconnect wires, again using a formulation that is compatible with GP or GGP.
3D Topologies for NetworksonChip
 in Proc. IEEE Int. SOC Conf., 2006
, 2006
"... Abstract—Several interesting topologies emerge by incorporating the third dimension in networksonchip (NoC). The speed and power consumption of 3D NoC are compared to that of 2D NoC. Physical constraints, such as the maximum number of planes that can be vertically stacked and the asymmetry betwe ..."
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Cited by 22 (0 self)
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Abstract—Several interesting topologies emerge by incorporating the third dimension in networksonchip (NoC). The speed and power consumption of 3D NoC are compared to that of 2D NoC. Physical constraints, such as the maximum number of planes that can be vertically stacked and the asymmetry between the horizontal and vertical communication channels of the network, are included in speed and power consumption models of these novel 3D structures. An analytic model for the zeroload latency of each network that considers the effects of the topology on the performance of a 3D NoC is developed. Tradeoffs between the number of nodes utilized in the third dimension, which reduces the average number of hops traversed by a packet, and the number of physical planes used to integrate the functional blocks of the network, which decreases the length of the communication channel, is evaluated for both the latency and power consumption of a network. A performance improvement of 40 % and 36 % and a decrease of 62 % and 58 % in power consumption is demonstrated for 3D NoC as compared to a traditional 2D NoC topology for a network size of aIPVand aPSTnodes, respectively. Index Terms—3D circuits, 3D integrated circuits (ICs), 3D integration, networksonchip (NoC), topologies.
Repeater Insertion in Tree Structured Inductive Interconnect
 IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
, 2001
"... Abstract – The effects of inductance on repeater insertion in RLC trees is the focus of this paper. An algorithm is introduced to insert and size repeaters within an RLC tree to optimize a variety of possible cost functions such as minimizing the maximum path delay, the skew between branches, or a c ..."
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Cited by 12 (2 self)
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Abstract – The effects of inductance on repeater insertion in RLC trees is the focus of this paper. An algorithm is introduced to insert and size repeaters within an RLC tree to optimize a variety of possible cost functions such as minimizing the maximum path delay, the skew between branches, or a combination of area, power, and delay. The algorithm has a complexity proportional to the square of the number of possible repeater positions and determines a repeater solution that is close to the global minimum. The repeater insertion algorithm is used to insert repeaters within several copperbased interconnect trees to minimize the maximum path delay based on both an RC model and an RLC model. The two buffering solutions are compared using the AS/X dynamic circuit simulator. It is shown that as inductance effects increase, the area and power consumed by the inserted repeaters to minimize the path delays of an RLC tree decreases. By including inductance in the repeater insertion methodology, the interconnect is modeled more accurately as compared to an RC model, permitting average savings in area, power, and delay of 40.8%, 15.6%, and 6.7%, respectively, for a variety of copperbased interconnect trees from a 0.25 μm CMOS technology. The average savings in area, power, and delay increases to 62.2%, 57.2%, and 9.4%, respectively, when using five times faster devices with the same interconnect trees. I.
Effects of global interconnect optimizations on performance estimation of deep submicron design
 in Proc. Int. Conf. on Computer Aided Design
, 2000
"... In this paper, we quantify the impact of global interconnect optimization techniques that address such design objectives as delay, peak noise, delay uncertainty due to noise, power, and cost. In doing so, we develop a new systemperformance simulation model as a set of studies within the MARCO GSRC ..."
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Cited by 11 (2 self)
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In this paper, we quantify the impact of global interconnect optimization techniques that address such design objectives as delay, peak noise, delay uncertainty due to noise, power, and cost. In doing so, we develop a new systemperformance simulation model as a set of studies within the MARCO GSRC Technology Extrapolation (GTX) system. We model a typical pointtopoint global interconnect and focus on accurate assessment of both circuit and design technology with respect to such issues as inductance, signal line shielding, dynamic delay, buffer placement uncertainty and repeater staggering. We demonstrate, for example, that optimal wire sizing models need to consider inductive effects – and that use of more accurate {1,3} worstcase capacitive coupling noise switch factors substantially increases peak noise estimates compared to traditional {0,2} bounds. We also find that optimal repeater sizes are significantly smaller than conventional models would suggest, especially when considering energydelay issues.
DTT: Direct Truncation of the Transfer Function  An Alternative to Moment Matching for Tree Structured Interconnect
 IEEE TRANS. COMPUTERAIDED DESIGN
, 2002
"... A method is introduced to evaluate time domain signals within RLC trees with arbitrary accuracy in response to any input signal. This method depends on finding a low frequency reducedorder transfer function by direct truncation of the exact transfer function at different nodes of an RLC tree. The m ..."
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Cited by 9 (0 self)
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A method is introduced to evaluate time domain signals within RLC trees with arbitrary accuracy in response to any input signal. This method depends on finding a low frequency reducedorder transfer function by direct truncation of the exact transfer function at different nodes of an RLC tree. The method is numerically accurate for any order of approximation, which permits approximations to be determined with a large number of poles appropriate for approximating RLC trees with underdamped responses. The method is computationally efficient with a complexity linearly proportional to the number of branches in an RLC tree. A common set of poles is determined that characterizes the responses at all of the nodes of an RLC tree which further enhances the computational efficiency. Stability is guaranteed by the DTT method for loworder approximations with less than five poles. Such loworder approximations are useful for evaluating monotone responses exhibited by RC circuits.
ModelOrder Reduction Using Variational Balanced Truncation with Spectral Shaping
"... This paper presents a spectrallyweighted balanced truncation technique for tightly coupled integated circuit interconnects, when the interconnect circuit parameters change as a result of statistical variations in the manufacturing process. The salient features of this algorithm are the inclusion of ..."
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Cited by 8 (0 self)
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This paper presents a spectrallyweighted balanced truncation technique for tightly coupled integated circuit interconnects, when the interconnect circuit parameters change as a result of statistical variations in the manufacturing process. The salient features of this algorithm are the inclusion of the parameter variation in the RLC interconnect, the guaranteed passivity of the reduced transfer function, and the availability of provable spectrallyweighted error bounds for the reducedorder system. This paper shows that the variational balanced truncation technique produces reduced systems that accurately follow the time and frequency domain responses of the original system when variations in the circuit parameters are taken into consideration. Experimental results show that the new variational spectrallyweighted balanced truncation attains, in average, 30 % more accuracy than the variational Krylovsubspacebased modelorder reduction techniques. 1
Sensitivity of Interconnect Delay to OnChip Inductance
, 2000
"... Inductance extraction has become an important issue in the design of high speed CMOS circuits. Two characteristics of onchip inductance are discussed in this paper that can significantly simplify the extraction of onchip inductance. The first characteristic is that the sensitivity of a signal wave ..."
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Cited by 6 (2 self)
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Inductance extraction has become an important issue in the design of high speed CMOS circuits. Two characteristics of onchip inductance are discussed in this paper that can significantly simplify the extraction of onchip inductance. The first characteristic is that the sensitivity of a signal waveform to errors in the inductance values is low, particularly the propagation delay and the rise time. It is quantitatively shown in this paper that the error in the propagation delay and rise time is below 9.4% and 5.9%, respectively, assuming a 30% relative error in the extracted inductance. If an RC model is used for the same example, the corresponding errors are 51% and 71%, respectively. The second characteristic is that the magnitude of the onchip inductance is a slowly varying function of the width of a wire and the geometry of the surrounding wires. These two characteristics can be exploited by using simplified techniques that permit approximate and sufficiently accurate values of th...
An Efficient Analytical Model of Coupled Onchip RLC Interconnects
"... In this paper, we present a new decoupled model for two coupled transmission lines with consideration of the inductive effect. It maps two coupled lines into two completely isolated lines with separated drivers and receivers, and has no loss of accuracy during the decoupling procedure. Further, we d ..."
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Cited by 5 (1 self)
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In this paper, we present a new decoupled model for two coupled transmission lines with consideration of the inductive effect. It maps two coupled lines into two completely isolated lines with separated drivers and receivers, and has no loss of accuracy during the decoupling procedure. Further, we derive a closedform time domain response for an isolated transmission line using a onesegment model. Combining the two models, we have an analytical timedomain solution to two coupled transmission lines. The model gives satisfied results for up to 5000 long lines when compared to SPICE simulation over an accurate distributed RLC circuit model, and can be used to model onchip wires in the layout design, logic synthesis and high level design. 1
Parasitic extraction: Current state of the art and future trends
 PROC. OF THE IEEE
, 2001
"... With the increase in circuit performance (higher speeds) and density (smaller feature size) in deep submicrometer (DSM) designs, interconnect parasitic effects are increasingly becoming more important. This paper first surveys the state of the art in parasitic extraction for resistance, capacitance, ..."
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Cited by 5 (1 self)
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With the increase in circuit performance (higher speeds) and density (smaller feature size) in deep submicrometer (DSM) designs, interconnect parasitic effects are increasingly becoming more important. This paper first surveys the state of the art in parasitic extraction for resistance, capacitance, and inductance. The paper then covers other related issues such as interconnect modeling, model order reduction, delay calculation, and signal integrity issues such as crosstalk. Some future trends on parasitic extraction, model reduction and interconnect modeling are discussed and a fairly complete list of references is given.
Improved A Priori Interconnect Predictions and Technology Extrapolation in the GTX System
 IEEE Trans. Very Large Scale Integr. (VLSI) Syst
, 2003
"... A priori interconnect prediction and technology extrapolation are closely intertwined. Interconnect predictions are at the core of technology extrapolation models of achievable system power, area density and speed. Technology extrapolation, in turn, informs a priori interconnect prediction via m ..."
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Cited by 3 (0 self)
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A priori interconnect prediction and technology extrapolation are closely intertwined. Interconnect predictions are at the core of technology extrapolation models of achievable system power, area density and speed. Technology extrapolation, in turn, informs a priori interconnect prediction via models of interconnect technology and interconnect optimizations. In this paper, we address the linkage between a priori interconnect prediction and technology extrapolation in two ways. First, we describe how rapid changes in technology, as well as rapid evolution of prediction methods, require a dynamic and flexible framework for technology extrapolation. We then develop a new tool, the GSRC Technology Extrapolation System (GTX), which allows capture of such knowledge and rapid development of new studies. Second, we identify several "nontraditional" facets of interconnect prediction and quantify their impact on key technology extrapolations. In particular, we explore the effects of interconnect design optimizations such as shield insertion, repeater sizing and repeater staggering, as well as modeling choices for RLC interconnects. Keywords # A priori interconnect prediction, technology extrapolation, VLSI, system performance models, interconnect delay, crosstalk noise, inductance. I.