We develop a robust, e#cient, and accurate tool, which integrates inductance extraction and simulation, called INDUCTWISE. This paper advances the state-of-the-art inductance extraction and simulation techniques and contains two major parts. In the first part, INDUCTWISE extractor, we discover the recently proposed inductance matrix sparsification algorithm, the K-method[1], albeit its great benefits of e#ciency, has a major flaw on the stability. We provide both a counter example and a remedy for it. A window section algorithm is also presented to preserve the accuracy of the sparsification method. The second part, INDUCTWISE simulator, demonstrates great e#ciency of integrating the nodal analysis formulation with the improved K-method. Experimental results show that INDUCTWISE has over 250x speedup compared to SPICE3. The proposed sparsification algorithm accelerates the simulator another 175x and speeds up the extractor 23.4x within 0.1% of error. INDUCTWISE can extract and simulate an 118K-conductor RKC circuit within 18 minutes. It has been well tested and released on the web for public usage. (http://vlsi.ece.wisc.edu/Inductwise.htm) 1.

The geometry-integration based vector potential equivalent circuit (VPEC) was introduced to obtain a localized circuit model for inductive interconnects in [1]. In this paper, we show that the method in [1] is accurate only for the two-body problem. We derive N-body VPEC models based on geometry integration and inversion of inductance matrix under the PEEC model, respectively. Both VPEC models are derived from first principles and are accurate compared to the full PEEC model. The resulting circuit matrix can be analyzed directly by existing simulation tools such as SPICE, and the simulation time of VPEC model is smaller than that for PEEC model for a bus structure with 256 wire segments. It is also passive and strictly diagonal dominant, which leads to efficient circuit sparsification methods such as numerical and geometry based sparsifications. Compared to the full PEEC model, the sparsified VPEC models are orders of magnitude faster and produce waveforms with very small error.

The recent demand for system-on-chip RF mixed-signal design and aggressive supply-voltage reduction require chip-level accurate analysis of both the substrate and power delivery systems. Together with the rising frequency, low-k dielectric, copper interconnects, and high conductivity substrate, the inductance e#ects raised serious concern recently. However, the increasing design complexity creates tremendous challenges for chip-level powerdelivery substrate co-analysis. In this paper, we propose a novel and e#cient reluctance-based passive model order reduction technique to serve these tasks. Our work, SuPREME(Substrate and Power-delivery Reluctance-Enhanced Macromodel Evaluation) not only greatly reduces the computational complexity of previous reluctance-based model order algorithms but is also capable of handling large number of noise sources e#ciently. To facilitate the analysis of inductive substrate return paths and evaluate the high-frequency substrate coupling e#ects, we derive a novel RLKC substrate model from Maxwell's equations for the first time. Experimental results demonstrate the superior runtime and accuracy of SuPREME compared to the traditional MNA-based simulation. 1.

In this paper, we report the developmentof the first commercial fullchip, three-dimensional, shapes-based, RLCK extraction tool, developed as part of a university-industry collaboration. The technique of return-limited inductances is used to provide a sparse, frequencyindependentinductanceand resistance network with self-inductances that represent sensible "nominal" values in the absence of mutual coupling. Mutual inductances are extracted for accurate noise analysis. The tool, AssuraRLCX, exploits high-capacity scan-bandtechniques and disk caching for inductance extraction as an extension to Cadence's existing Assura RCX extractor. 1

The ability to compute the parasitic inductance of the interconnect is critical to the timing verification of modern VLSI circuits. A challenging aspect of inductance extraction is the solution of large, dense, complex linear systems of equations via iterative methods. Accelerating the convergence of the iterative method through preconditioning is made difficult due to the non-availability of the system matrix. This paper presents a novel algorithm to solve these linear systems by restricting current to a discrete solenoidal subspace in which Kirchoff's law is obeyed, and solving a reduced system via an iterative method such as GMRES. A preconditioner based on the Green's function is used to achieve near-optimal convergence rates in several cases. Experiments on a number of benchmark problems illustrate the advantages of the proposed method over FastHenry.

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In this paper, a precorrected-FFT approach for fast and highly accurate simulation of circuits with on-chip inductance is proposed. This work is motivated by the fact that circuit analysis and optimization methods based on the partial element equivalent circuit (PEEC) model require the solution of a subproblem in which a dense inductance matrix must be multiplied by a given vector, an operation with a high computational cost. Unlike traditional inductance extraction approaches, the precorrected-FFT method does not attempt to compute the inductance matrix explicitly, but assumes the entries in the given vector to be the fictitious currents in inductors and enables the accurate and quick computation of this matrix-vector product by exploiting the properties of the inductance calculation procedure. The effects of all of the inductors are implicitly considered in the calculation: faraway inductor effects are captured by representing the conductor currents as point currents on a grid, while nearby inductive interactions are modeled through direct calculation. The grid representation enables the use of the discrete Fast Fourier Transform (FFT) for fast magnetic vector potential calculation. The precorrected-FFT method has been applied to accurately simulate large industrial circuits with up to 121,000 inductors and over 7 billion mutual inductive couplings in about 20 minutes. Techniques for trading off CPU time with accuracy using different approximation orders and grid constructions are also illustrated. Comparisons with a block diagonal sparsification method are used to illustrate the accuracy and effectiveness of this method. In terms of accuracy, memory and speed, it is shown that the precorrected-FFT method is an excellent approach for simulating on-chip inductance...

Inductive and capacitive coupling effects for high-speed global interconnects are studied via simulation. The impact of inductive coupling on delay and noise is found to be comparable to capacitive effects in high-speed buses. The results indicate that current-return paths are not strictly bounded by wide VDD/GND lines, so that inductive coupling is only partially eliminated by using shield wires. Shielding strategies for noise- and delay-sensitive nets is proposed, considering worst-case switching patterns.

Abstract—High-speed digital design is becoming increasingly analog. In particular, interconnect response at high frequencies can be nonmonotonic with “porch steps ” and ringing. Crosstalk (both capacitive and inductive) can result in glitches on wires that can produce functional failures in receiving circuits. Most of these important effects are not addressed with traditional automatic test pattern generation (ATPG) and built-in self-test (BIST) techniques, which are limited to the binary abstraction. In this work, we explore the feasibility of integrating primitive sampling oscilloscopes on-chip to provide waveforms on selective critical nets for test and diagnosis. The oscilloscopes rely on subsampling techniques to achieve 10-ps timing accuracy. High-speed samplers are combined with delay-locked loops (DLLs) and a simple 8-bit analog-to-digital converter (ADC) to convert the waveforms into digital data that can be incorporated as part of the chip scan chain. We will describe the design and measurement of a chip we have fabricated to incorporate these oscilloscopes with a high-frequency interconnect structure in a TSMC 0.25- m process. The layout was extracted using Cadence’s Assura RCX-PL extraction engine, enabling a comparison between simulated and measured results. Index Terms—Inductance modeling, mixed-signal test, subsampling. I.

Abstract — With the advancement of radio frequency mixedsignal ICs, lossy silicon substrate has significant impact on the already complicated interconnect modeling issue. To account for the substrate loss, the traditional electromagnetic methods are often computationally prohibitive for large scale VLSI geometries. In this paper, we extend the traditional PEEC model to consider the substrate eddy current loss based on the complex image theory and the skin and proximity effects by discretization of conductors. To deal with even larger scale of interconnects, we present a reluctance based model, ESPRIT, to enhance the extended PEEC model to use reluctance by equipping it with an advanced windowing algorithm to further reduce the model size and runtime. Detail comparisons with state-of-the-art tools such as FastHenry and Momentum demonstrate that ESPRIT is within 1 % accuracy while providing over 100X speedup. I.