Abstract. Recent advances in electronic technology and integration coupled with increasing needs for more services in portable communications favors the development of high performance dual- mode terminals. Here, we present the complete low-power architecture implementation of the GMSK/GFSK modulator/demodulator including the FIR filters, developed for the purposes of the LPGD project. The main features of the modulator/demodulator and the architectural implementation of FIR filters are described. The interface with ASPIS processor and A/D & D/A converters are also described in detail manner. Measurements from a prototype FPGA implementation, prove the modem’s sufficiency in terms of telecommunication issues, as wells as its lowpower consumption.

Abstract: In this report the design and the innovative low-power design steps followed for the development of a DCS1800-GSM/DECT modem are presented. This includes a low complexity telecommunication algorithms, a low power synthesis technique for the realisation of FIR filters, an application-specific behavioural level power management and a dynamic frequency reduction scheme. The complete low power architecture design as well as the measured performance metrics are also presented. Copyright © 1999 INTRACOM

In this paper, we propose a reduced complexity and power efficient System-on-Chip (SoC) architecture for adaptive interference suppression in CDMA systems. The adaptive Parallel-Residue-Compensation architecture leads to significant performance gain over the conventional interference cancellation algorithms. The multi-code commonality is explored to avoid the direct Interference Cancellation (IC), which reduces the IC complexity from O(K 2 N) to O(KN). The physical meaning of the complete versus weighted IC is applied to clip the weights above a certain threshold so as to reduce the VLSI circuit activity rate. Novel scalable SoC architectures based on simple combinational logic are proposed to eliminate dedicated multipliers with at least 10 × saving in hardware resource. A Catapult C High Level Synthesis methodology is apply to explore the VLSI design space extensively and achieve at least 4 × speedup. Multi-stage Convergence-Masking-Vector combined with clock gating is proposed to reduce the VLSI dynamic power consumption by up to 90%.

Portable terminals supporting the Digital Enhanced Cordless Telecommunications (DECT) standard have entered the world market the last few years. For such devices low energy dissipation is of critical importance. In this paper the design of a low-power fully digital baseband receiver that embodies innovative and conventional low-power optimizations is presented. The proposed baseband receiver complies with the DECT standard as far as digital modem functions are concerned. The developed energy-conscious, low complexity DECT demodulation algorithm and the low-power hardware architecture are described in a detailed manner.