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Considering Testability at Behavioral Level: Use of Transformations for Partial Scan Cost Minimization Under Timing and Area Constraints
 IEEE Trans. on CAD
, 1995
"... We address the problem of transforming a behavioral specification so that synthesis of a testable implementation from the new specification requires significantly less area and partial scan cost than synthesis from the original specification. The proposed approach has three components: a library of ..."
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Cited by 10 (4 self)
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We address the problem of transforming a behavioral specification so that synthesis of a testable implementation from the new specification requires significantly less area and partial scan cost than synthesis from the original specification. The proposed approach has three components: a library of relevant transformation mechanisms, an objective function, and an optimization algorithm. The most effective transformations for testability optimization are identified by analyzing the fundamental relationship between transformational mechanisms and topological and functional properties of the computations that affect testability. A dynamic, twostage objective function that estimates the area and testability of the final implementation, and also captures enabling and disabling effects of the transformations, is developed. Optimization is done using a new randomized branch and bound steepest descent algorithm. Application of the transformation algorithm on several benchmark examples demonstrates significant simultaneous improvement in both area and testability of the final implementations.
PotentialDriven Statistical Ordering of Transformations
, 1997
"... Successive, well organized application of transformations has been widely recognized as an exceptionally effective, but complex and difficult CAD task. We introduce a new potentialdriven statistical approach for ordering transformations. Two new synthesis ideas are the backbone of the approach. The ..."
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Cited by 9 (5 self)
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Successive, well organized application of transformations has been widely recognized as an exceptionally effective, but complex and difficult CAD task. We introduce a new potentialdriven statistical approach for ordering transformations. Two new synthesis ideas are the backbone of the approach. The first idea is to quantify the characteristics of all transformations and the relationship between them based on their potential to reorganize a computation such that the complexity of the corresponding implementation is reduced. The second one is based on the observation that transformations may disable each other not only because they prevent the application of the other transformation, but also because both transformations target the same potential of the computation. These two observations drastically reduce the search space to find efficient and effective scripts for ordering transformations. A key algorithmic novelty is that both conceptual and optimization insights as well as all opti...
Partial Scan Selection for UserSpecified Fault Coverage
 In European Design Automation Conference
, 1995
"... With current approaches to partial scan, it is difficult, and often impossible, to achieve a specific level of fault coverage without returning to full scan. In this paper, we introduce a new formulation of the minimum scan chain assignment problem and propose an effective covering algorithm and tes ..."
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Cited by 1 (1 self)
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With current approaches to partial scan, it is difficult, and often impossible, to achieve a specific level of fault coverage without returning to full scan. In this paper, we introduce a new formulation of the minimum scan chain assignment problem and propose an effective covering algorithm and test sequence generator SCORCH (Scan Chain Ordering with Reduced Cover Heuristic) to solve it. SCORCH uses a combinational test generator not only to optimize the scan chain assignment, subject to maintaining a userspecified level of fault coverage, but also as a basis for the test sequence generation. We report experimental results with minimized partial scan assignment and 100% fault coverage for a set of large benchmarks. I. Introduction A test strategy based on full scan design can typically achieve 100% fault coverage at an acceptable cost of test generation. The drawback may be the cost in reduced performance, increased area and longer test application time. A partial scan design app...
A Comprehensive Partial Scan Chain Assignment and Test Generation
, 1995
"... Current approaches to partial scan may not necessarily cover all faults, in particular the faults introduced by the partial scan chain (or the test machine) itself. Typically, the user does not have complete control on the fault coverage achieved by the partial scan. In this paper, we introduce a ne ..."
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Current approaches to partial scan may not necessarily cover all faults, in particular the faults introduced by the partial scan chain (or the test machine) itself. Typically, the user does not have complete control on the fault coverage achieved by the partial scan. In this paper, we introduce a new partial scan assignment algorithm that not only ensures userspecified coverage of all target faults in the object machine but also effectively addresses the complete coverage of faults in the test (or partial scan) machine. The algorithm allows a tradeoff of increased test application time to reduce scan chain size, while maintaining a userspecified level of fault coverage. For a given scan chain, a single application of a test sequence may not detect a particular fault. We raise the probability of detecting the fault by repeating the test sequence. Experimental results on large sequential benchmark circuits demonstrate that the model we use predicts this tradeoff consistently and accu...
Optimizing Designs Using the Addition of Deflection Operations
"... Abstract—This paper introduces hot potato behavioral synthesis transformation techniques. These techniques add deflection operations in the behavioral description of a computation in such a way that the requirements for two important components of the final implementation cost, the number of registe ..."
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Abstract—This paper introduces hot potato behavioral synthesis transformation techniques. These techniques add deflection operations in the behavioral description of a computation in such a way that the requirements for two important components of the final implementation cost, the number of registers and the number of interconnects, are significantly reduced. Moreover, we demonstrate how hot potato techniques can be effectively used during behavioral synthesis to minimize the partial scan overhead to make the synthesized design testable. Index Terms—Digital system testing, highlevel synthesis, optimization, sequential logic circuit. I.
Hot Potato Techniques in High Level Synthesis
, 1995
"... This paper introduces hot potato high level synthesis transformation techniques. These techniques add deflection operations in the behavioral description of a computation in such a way that the requirements for two important components of the final implementation cost, the number of registers and th ..."
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This paper introduces hot potato high level synthesis transformation techniques. These techniques add deflection operations in the behavioral description of a computation in such a way that the requirements for two important components of the final implementation cost, the number of registers and the number of interconnects, are significantly reduced. Moreover, it is shown how hot potato techniques can be effectively used during high level synthesis to minimize the partial scan overhead to make the synthesized design testable. The paper presents theoretical foundations, efficient algorithms and experimental results which indicate the wide application range and effectiveness of the new transformation technique for behavioral level synthesis. 1.0 Introduction 1.1 Transformations in High Level Synthesis Computational transformations are alternations in the structure of controldata flow graph (CDFG) so that the functionality of the initial specification is maintained [Fis88, Wal91]. Tran...
Techniques for Implementation of AtSpeed Testable, High Performance, and Low Cost Linear Designs
, 1995
"... Linear computations are most widely used type of ASIC computations. Due to their exceptional theoretical tractability and practical importance, numerous schemes for their implementatinn have been proposed. The canonical schemes have been widely studied and evaluated according to a number of importan ..."
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Linear computations are most widely used type of ASIC computations. Due to their exceptional theoretical tractability and practical importance, numerous schemes for their implementatinn have been proposed. The canonical schemes have been widely studied and evaluated according to a number of important criteria, including the number of operations, number of bits, area, throughput and latency, and power metrics. However, until now the testability of linear systems was not studied. After we show that all the most widely used implementation strutctures require a significant test ing related cost, we derive a new structure which is amenable for atspeed testing with no additional hardware overhead. Furthermore, the new structure provides a high throughput, low cost, and low power implementation for an arbitrary linear computation. The key technical novelties of the paper is a novel approach for use of transformations and coordinate use of transformations and sc]heduling for producing highly testable implementations.