We present an algorithm for accurately controlling delays during the placement of large standard cell integrated circuits. Previous approaches to timing driven placement could not handle circuits containing 20,000 or more cells and yielded placement qualities which were well short of the state of the art. Our timing optimization algorithm has been added to the placement algorithm which has yielded the best results ever reported on the full set of MCNC benchmark circuits, including a circuit containing more than 100,000 cells. A novel pin-pair algorithm controls the delay without the need for user path specification. The timing algorithm is generally applicable to hierarchical, itera-tive placement methods. Using this algorithm, we present results for the only MCNC standard cell benchmark circuits (fract, struct, and avq.small) for which timing information is available. We decreased the delay of the longest path of circuit fract by 36 % at an area cost of only 2.5%. For circuit struct, the delay of the longest path was decreased by 50 % at an area cost of 6%. Finally, for the large (21,000 cell) circuit avq.small, the longest path delay was decreased by 28 % at an area cost of 6%.

Interconnect has become the dominating factor in determining circuit performance and reliability in deep submicron designs. In this embedded tutorial, we first discuss the trends and challenges of interconnect design as the technology feature size rapidly decreases towards below 0.1 micron. Then, we present commonly used interconnect models and a set of interconnect design and optimization techniques for improving interconnect performance and reliability. Finally, we present comparisons of different optimization techniques in terms of their efficiency and optimization results, and show the impact of these optimization techniques on interconnect performance in each technology generation from the 0.35µm to 0.07µm projected in the National Technology Roadmap for Semiconductors.

We present critical-sink routing tree (CSRT) constructions which exploit available critical-path information to yield high-performance routing trees. Our CS-Steiner and "Global Slack Removal" algorithms together modify traditional Steiner tree constructions to optimize signal delay at identified critical sinks. We further propose an iterative Elmore routing tree (ERT) construction which optimizes Elmore delay directly, as opposed to heuristically abstracting linear or Elmore delay as in previous approaches. Extensive timing simulations on industry IC and MCM interconnect parameters show that our methods yield trees that significantly improve (by averages of up to 67%) over minimum Steiner routings in terms of delays to identified critical sinks. ERTs also serve as generic high-performance routing trees when no critical sink is specified: for 8-sink nets in standard IC (MCM) technology, we improve average sink delay by 19% (62%) and maximum sink delay by 22% (52%) over the mini...

We present two critical-sink routing tree (CSRT) constructions which exploit critical-path information that becomes available during timing-driven layout. Our CS-Steiner heuristics with "Global Slack Removal" modify traditional Steiner constructions and produce routing trees with significantly lower criticalsink delays compared with existing performance-driven methods. We also propose a new class of Elmore routing tree (ERT) constructions, which iteratively add tree edges to minimize Elmore delay. This direct optimization of Elmore delay yields trees that improve delays to identified critical sinks by up to 69 % over minimum Steiner routings. ERTs also improve performance over such recent methods as [1] [6] when no critical sinks are specified.

Motivated by analysis of distributed RC delay in routing trees, we propose a new tree construction for performance-driven global routing which directly trades off between Prim's minimum spanning tree algorithm and Dijkstra's shortest path tree algorithm. This direct combination of two objective functions and their corresponding optimal algorithms contrasts with the more indirect "shallow-light" methods of [2, 4, 10]. Our method achieves routing trees which satisfy a given routing tree radius bound while using less wire than previous methods. Detailed simulations show that this wirelength savings translates into significantly improved delay over both the method of [4] and standard MST routing in both IC and multi-chip module (MCM) interconnect technologies.

With feature-sizes below 0�25µm, interconnect delays account for over 40 % of worst delays [12]. Transitions to 0�18µm and 0�13µm further increase this figure, and thus the relative importance of timing-driven placement for VLSI. Our work introduces a novel minimization of maximal path delay that improves upon previously known algorithms for timing-driven placement. Our placement algorithms have provable properties and are fast in practice. Our empirical validation is based on extending a scalable min-cut placer with proven empirical record in wirelength- and congestion-driven placement [4]. The overhead of timing-driven placement was within 50 % CPU time. We placed industrial circuits and evaluated the layouts with a commercial static timing analyzer.

In this paper, we present an optimal algorithm for solving the simultaneous technology mapping and linear placement problem for tree-structured circuits with the objective of minimizing the post-layout area. The proposed algorithm relies on generation of gate-area versus cut-width curves using a dynamic programming approach. A novel design flow, which extends this algorithm to minimize the circuit delay and handle general DAG structures, is also presented. Experimental results on MCNC benchmarks are reported.

In this paper, we present a timing-driven global router for symmetrical-array-based FPGAs. The routing resources in the symmetrical-array-based FPGAs consist of segments of various lengths. Researchers have shown that the number of segments, instead of wirelength, used by a net is the most critical factor in controlling routing delay in an FPGA. Thus, traditional measure of routing delay based on the geometric distance of a signal is not accurate. To consider wirelength and delay simultaneously, we study a model of timing-driven routing trees, arising from the special properties of FPGA routing architectures. We explore the complexity of the routingtree problem and present efficient and effective approximation algorithms for the problem. Based on the solutions to the routing-tree problem, we present a global-routing algorithm which is able to utilize various routing segments with global consideration to meet the timing constraints. Experimental results on benchmark circuits show that o...

this article, we use the word "scalability" in the practical, operational sense and therefore consider not just ) algorithms but rather any framework likely to have applicability lasting for several technology generations and circuit-size ranges

We survey our recent work in the analysis and design of interconnect topologies for high-speed VLSI. Results include: a new, fast distributed RLC analysis method based on a two-pole approximation; an A-tree formulation for performance-driven interconnect; an optimal wiresizing algorithm; and new critical-path dependent routing tree algorithms. 1 Introduction Interconnection design is becoming a major concern in the design of high-speed systems, where state-of-the-art integrated circuits use submicron technology and operate at multi-giga hertz clock rates. In this range, optimization based on the traditional layout design objective, i.e. minimization of chip area, no longer suffices since the emphasis on system performance requires different consideration. For instance, the minimum Steiner tree has traditionally been the preferred interconnect topology because: (1) it uses the minimum wiring area and (2) minimum wiring area results in minimum wire capacitance, which is the dominant fac...