We propose a reflective model to express and to automatically manage dependencies between objects. This model describes reflective facilities which enable the changing of language semantics. Although the importance of inter-object dependencies is well accepted, there is only limited object-oriented language support for their specification and implementation. In response to this lack of expressiveness of object models, the flo language integrates dependency management into the object oriented paradigm. Dependencies are described as first class objects and flo automatically maintains the consistency of the dependency graph.

This paper describes the design and implementation of a high-level visualization programming system called Viz. Viz was created out of a need to support rapid visualization prototyping in an environment that could be extended by abstractions in the application problem domain. Viz provides this in a programming environment built on a high-level, interactive language (Scheme) that embeds a 3D graphics library (Open Inventor), and that utilizes a data reactive model of visualization operation to capture mechanisms that have been found to be important in visualization design (e.g., constraints, controlled data flow, dynamic analysis, animation). The strength of Viz is in its ability to create non-trivial visualizations rapidly and to construct libraries of 3D graphics functionality easily. Although our original focus was on parallel program and performance data visualization, Viz applies beyond these areas. We show several examples that highlight Viz functionality and the visualization des...

. We propose an object-oriented approach for the formal verification of processors. This approach has been validated on significant applications. It is based on a class hierarchy that provides the basic components to describe processors at any abstraction level, and to specify verifications to execute. The originality of our method is to combine an object-oriented model (to ensure genericity) and a computer algebra verification system (to ensure efficiency). Computer experiments with our framework clearly shown three main advantages: processor descriptions are very easy to write down, the core of the verification system is generic so it may be applied without any modification to different processors, and last, the proof times are very short compared with previous approaches. 1 Introduction In this section, we first provide general motivations for hardware verification, and then outline our approach in general terms. 1.1 Motivations In order to produce correct circuits, s...

ion (du monde r#el) [11]. Cette approche permet de proposer une architecture originale dans des mondes homog#nes o# tout composant peut #tre d#crit par des d#pendances ou en mondes h#t#rog#nes o# l'int#gration d'un gestionnaire de dialogue devient n#cessaire. Ces travaux ont donn# lieu # plusieurs pr#sentations dans le cadre des GDR et # un d#but de collaboration avec une #quipe du CNET Sophia. A Controler P C P C graphical object 1 graphical object 2 constraints rules P P C graphical object 1 graphical object 2 A PAC Hierarchy The FLO Implementation A Controler C C constraints rules C A PAC Hierarchy The FLO Implementation A A application object 1 application object 2 application object 1 application object 2 A A Figure 5: Mod#lisation FLO de PAC 2.3.5 Contraintes r#actives pour les interfaces graphiques L'utilisation de contraintes pour la r#alisation d'interfaces graphiques constitue une extension au mod#le propos# par P. Franchi, dans les ann#es 88-92, pour g#n#rer des IHM par gra...

We propose a framework for the specification and formal verification of processors, based on generic interpreters. The originality of our method is to combine a generic specification environment and an efficient verification system. Computer experiments with our framework have clearly shown three main advantages: processor descriptions are concise and very easy to write down, the core of the verification system is generic so it may be applied without any modification to different processors, and last, the proof times are very short compared with previous approaches. Keywords: Automatic verification of hardware descriptions, very high level specification techniques and tools, formal systems for reasoning about hardware. 1 Introduction 1.1 Motivations In order to produce correct circuits, attention has been paid these last ten years on formal verification methods (for a survey and further justifications see [12]). Formally verifying a circuit consists in proving that its specif...

Cutting-edge 3D real-time rendering is where programmers rack their brains to feed more instructions to CPU or transfer more data on the bus within each frame, and dynamic languages seem to have no place there. However, there is another hidden cost which is growing rapidly as the quality and complexity of rendered images get higher—the cost of content creation. At SIGGRAPH 2000 and 2001, we, Square USA R&D team showed real-time rendering of scenes from full computergenerated movie “Final Fantasy: The Spirits Within”. Although we used the most advanced rendering hardware at that time, such as Sony Computer Entertainment’s GSCube parallel rendering engine and nVidia’s Quadro DCC chip, we had to spend lots of time to tune data to achieve the maximum image quality. We found it tremendous help to have an embedded Scheme interpreter in real-time rendering engine. Scheme could lay out the data on the memory, inspect the state of the engine, and handle user interactions and allow data manipulation over the network, without affecting rendering performance. Scheme representation of the scene structure worked nicely for the last-minute tuning (lots of Emacs works, in fact). 1