An adaptive algorithm, whose step complexity adjusts to the number of active processes, is attractive for situations in which the number of participating processes is highly variable. This paper studies the number and type of multiwriter registers that are needed for adaptive algorithms. We prove that if a collect algorithm is f-adaptive to total contention, namely, its step complexity is f(k), where k is the number of processes that ever tooka step, then it uses Ω(f −1 (n)) multi-writer registers, where n is the total number of processes in the system. Furthermore, we show that competition for the underlying registers is inherent for adaptive collect algorithms. We consider c-write registers, to which at most c processes can be concurrently about to write. Special attention is given to exclusive-write registers, the case c = 1 where no competition is allowed, and concurrent-write registers, the case c = n where any amount of competition is allowed. A collect algorithm is f-adaptive to point contention, if its step complexity is f(k), where k is the maximum number of simultaneously active processes. Such an algorithm is shown to require Ω(f −1 ( n c)) concurrent-write registers, even if an un-limited number of c-write registers are available. A smaller lower bound is also obtained in this situation for collect algorithms that are f-adaptive to total contention. The lower bounds also hold for nondeterministic implementations of sensitive objects from historyless objects. Finally, we present lower bounds on the step complexity in solo executions (i.e., without any contention), when only c-write registers are used: For weaktest&set objects, we log n present an Ω() lower bound. Our lower bound log c+log log n for collect and sensitive objects is Ω ( n−1 c).

Abstract. We introduce a novel term, memory-adaptive, that intuitively captures what it means for a distributed protocol to most efficiently make use of its shared memory. We also prove three results that relate to our memory-adaptive model. In our store/release protocols processors are required to store a value in shared MWMR memory so that it cannot be overwritten until it has been released by the processor. We show that there do not exist uniformly wait-free store/release protocols using only the basic operations read and write that are memory-adaptive to point contention. We further show that there exists a uniformly waitfree store/release protocol using only the basic operations read and write that is memory-adaptive to total contention. We finally show that there exists a uniformly wait-free store/release protocol using only the basic operations read, write, and write-plus that is memory-adaptive to interval contention and time-adaptive to total contention. 1

this paper do