Abstract — Process variations are of increasing concern in today’s technologies, and can significantly affect circuit performance. We present an efficient statistical timing analysis algorithm that predicts the probability distribution of the circuit delay considering both inter-die and intra-die variations, while accounting for the effects of spatial correlations of intra-die parameter variations. The procedure uses a first-order Taylor series expansion to approximate the gate and interconnect delays. Next, principal component analysis techniques are��and ��� are employed to transform the set of correlated parameters into an uncorrelated set. The statistical timing computation is then easily performed with a PERT-like circuit graph traversal. The run-time of our algorithm is linear in the number of gates and interconnects, as well as the number of varying parameters and grid partitions that are used to model spatial correlations. The accuracy of the method is verified with Monte Carlo simulation. On average, for 100nm technology, the errors of mean and standard deviation values computed by the proposed method respectively, and the errors of predicting the��and confidence point are ���and ���respectively. A testcase with about 17,800 gates was solved in about�seconds, with high accuracy as compared to a Monte Carlo simulation that required more than�hours.

Traditionally, fault tolerance researchers have required architectural state to be numerically perfect for program execution to be correct. However, in many programs, even if execution is not 100 % numerically correct, the program can still appear to execute correctly from the user’s perspective. Hence, whether a fault is unacceptable or benign may depend on the level of abstraction at which correctness is evaluated, with more faults being benign at higher levels of abstraction, i.e. at the user or application level, compared to lower levels of abstraction, i.e. at the architecture level. The extent to which programs are more fault resilient at higher levels of abstraction is application dependent. Programs that produce inexact and/or approximate outputs can be very resilient at the application level. We call such programs soft computations, and we find they are common in multimedia workloads, as well as artificial intelligence (AI) workloads. Programs that compute exact numerical outputs offer less error resilience at the application level. However, we find all programs studied in this paper exhibit some enhanced fault resilience at the application level, including those that are traditionally considered exact computations– e.g., SPECInt CPU2000. This paper investigates definitions of program correctness that view correctness from the application’s standpoint rather than the architecture’s standpoint. Under application-level correctness, a program’s execution is deemed correct as long as the result it produces is acceptable to the user. To quantify user satisfaction, we rely on application-level fidelity metrics that capture userperceived program solution quality. We conduct a detailed fault susceptibility study that measures how much more fault resilient programs are when defining correctness at the

Transistor threshold voltages (V th ) have been reduced as part of on-going technology scaling. The smaller V th values feature increased variations due to underlying process variations, with a strong within-die component. Correspondingly, given the exponential dependence of leakage on V th , circuit leakage currents are increasing significantly and have strong within-die statistical variations. With these leakage currents loading the power grid, the grid develops correspondingly large statistical voltage drops. This leakage-induced voltage drop is an unavoidable background level of noise on the grid. Any additional non-leakage currents due to circuit activity will lead to voltage drop which is to be added to this background noise. We propose a technique for checking whether the statistical voltage drop on every node is within user-specified bounds, given user-specified statistics of the leakage currents.

We develop architectural techniques for mitigating the impact of process variability. Our techniques hide the performance effects of slow components—including registers, functional units, and L1I and L1D cache frames—without slowing the clock frequency or pessimistically assuming that all components are slow. Using ideas previously developed for other purposes—criticality-based allocation of resources, prefetching, and prefetch buffering—we allow design engineers to aggressively set the clock frequency without worrying about the subset of components that cannot meet this frequency. Our techniques outperform speed binning, because clock frequency benefits outweigh slight losses in IPC.

Abstract — We present a new linear time technique to compute criticality information in a timing graph by dividing it into “zones”. Errors in using tightness probabilities for criticality computation are dealt with using a new clustering based pruning algorithm which greatly reduces the size of circuitlevel cutsets. Our clustering algorithm gives a 150X speedup compared to a pairwise pruning strategy in addition to ordering edges in a cutset to reduce errors due to Clark’s MAX formulation. The clustering based pruning strategy coupled with a localized sampling technique reduces errors to within 5 % of Monte Carlo simulations with large speedups in runtime. I. INTRODUCTION AND PREVIOUS WORK With scaling of technology, process parameter variations render the circuit delay as unpredictable [6], making sign-off ineffective in assuring against chip failure. Recent works concerning Statistical Static Timing Analysis (SSTA) in [1], [9] deal with this issue by treating the delay of gates and

As computer architects, we frequently analyze the performance of systems, and we have developed well-understood metrics for reporting and comparing system performances. The dominant textbook in our field [7] is subtitled

I would like to thank my advisor, Prof. Abhijit Chatterjee, for accepting me in his research group and for his support and guidance during the course of my research. I could not have imagined a better advisor for my PhD. I am also thankful to Prof. Adit Singh. His continuous help and insights had a significant impact on the research presented here. I also would like to thank my committee members, Dr. Sudhakar Yalamanchili, Dr. Jeff Davis, and Dr. Linda Milor for taking the time to serve on my proposal and defense committees. I would like to acknowledge the help and support of my past and present lab-mates. I need to especially thank Utku Diril for patiently answering many of my questions and helping me even after he graduated from Georgia Tech. I would also like to thank Gigasale Research Center (GSRC) and National Science Foundation (NSF) for funding this research and providing different venues for interacting with industry experts and getting their valuable inputs. Finally, I would like to thank the members of the department staff (in particular from the administrative, financial, and IT offices) for their extraordinary patience and

Traditionally, fault tolerance researchers have required architectural state to be numerically perfect for program execution to be correct. However, in many programs, even if execution is not 100 % numerically correct, the program can still appear to execute correctly from the user’s perspective. Hence, whether a fault is unacceptable or benign may depend on the level of abstraction at which correctness is evaluated, with more faults being benign at higher levels of abstraction, i.e. at the user or application level, compared to lower levels of abstraction, i.e. at the architecture level. The extent to which programs are more fault resilient at higher levels of abstraction is application dependent. Programs that produce inexact and/or approximate outputs can be very resilient at the application level. We call such programs soft computations, and we find they are common in multimedia workloads, as well as artificial intelligence (AI) workloads. Programs that compute exact numerical outputs offer less error resilience at the application level. However, we find all programs studied in this paper exhibit some enhanced fault resilience at the application level, including those that are traditionally

Abstract not found

Abstract — With ever shrinking device geometries, process variations play an increased role in determining the delay of a digital circuit. Under such variations, a gate may lie on the critical path of a manufactured die with a certain probability, called the criticality probability. In this paper, we present a new technique to compute the statistical criticality information in a digital circuit under process variations by linearly traversing the edges in its timing graph and dividing it into “zones”. We investigate the sources of error in using tightness probabilities for criticality computation with Clark’s statistical maximum formulation. The errors are dealt with using a new clustering based pruning algorithm which greatly reduces the size of circuit-level cutsets improving both accuracy and runtime over the current state of the art. On large benchmark circuits, our clustering algorithm gives about a 250X speedup compared to a pairwise pruning