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Structuring and Automating Hardware Proofs in a HigherOrder TheoremProving Environment
 Formal Methods in System Design
, 1993
"... . In this article we present a structured approach to formal hardware verification by modelling circuits at the registertransfer level using a restricted form of higherorder logic. This restricted form of higherorder logic is sufficient for obtaining succinct descriptions of hierarchically design ..."
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Cited by 20 (7 self)
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. In this article we present a structured approach to formal hardware verification by modelling circuits at the registertransfer level using a restricted form of higherorder logic. This restricted form of higherorder logic is sufficient for obtaining succinct descriptions of hierarchically designed registertransfer circuits. By exploiting the structure of the underlying hardware proofs and limiting the form of descriptions used, we have attained nearly complete automation in proving the equivalences of the specifications and implementations. A hardwarespecific tool called MEPHISTO converts the original goal into a set of simpler subgoals, which are then automatically solved by a generalpurpose, firstorder prover called FAUST. Furthermore, the complete verification framework is being integrated within a commercial VLSI CAD framework. Keywords: hardware verification, higherorder logic 1 Introduction The past decade has witnessed the spiralling of interest within the academic com...
Formal Synthesis in Circuit Design  A Classification and Survey
, 1996
"... . This article gives a survey on different methods of formal synthesis. We define what we mean by the term formal synthesis and delimit it from the other formal methods that can also be used to guarantee the correctness of an implementation. A possible classification scheme for formal synthesis m ..."
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Cited by 13 (2 self)
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. This article gives a survey on different methods of formal synthesis. We define what we mean by the term formal synthesis and delimit it from the other formal methods that can also be used to guarantee the correctness of an implementation. A possible classification scheme for formal synthesis methods is then introduced, based on which some significant research activities are classified and summarized. We also briefly introduce our own approach towards the formal synthesis of hardware. Finally, we compare these approaches from different points of view. 1 Introduction In everyday use, synthesis means putting together of parts or elements so as to make up a complex whole. However in the circuit design domain, synthesis stands for a stepwise refinement of circuit descriptions from higher levels of abstraction (specifications) to lower ones (implementations), including optimizations within one abstraction level. Synthesis can be performed by hand for small circuits. Nowadays mor...
A Transformational Approach to Formal Digital System Design
, 1993
"... syntax for design annotations : : : : : : : : : : : : : : : : : 45 4.3 Semantic algebras for design annotations : : : : : : : : : : : : : : : : 46 4.4 Semantic algebras, continued : : : : : : : : : : : : : : : : : : : : : : : 47 4.5 Valuation functions for design annotations : : : : : : : : : : : : ..."
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Cited by 10 (0 self)
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syntax for design annotations : : : : : : : : : : : : : : : : : 45 4.3 Semantic algebras for design annotations : : : : : : : : : : : : : : : : 46 4.4 Semantic algebras, continued : : : : : : : : : : : : : : : : : : : : : : : 47 4.5 Valuation functions for design annotations : : : : : : : : : : : : : : : 48 4.6 Devices : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 50 5.1 Constant dummy in the basic library : : : : : : : : : : : : : : : : : : 58 5.2 Interconnection devices in the basic library : : : : : : : : : : : : : : : 58 5.3 Devices in the comp library : : : : : : : : : : : : : : : : : : : : : : : 59 5.4 Timing analysis of the design in session box 7 : : : : : : : : : : : : : 66 5.5 Scheduling the design in session box 7 : : : : : : : : : : : : : : : : : : 67 5.6 The design after session box 8 : : : : : : : : : : : : : : : : : : : : : : 68 5.7 The design after session box 15 : : : : : : : : : : : : : : : : : : : : : 74 5.8 The design after session box 16 : : :...
Performing HighLevel Synthesis via Program Transformations within a Theorem Prover
 In: Digital System Design Workshop at the 24th EUROMICRO 98 Conference
, 1998
"... In this paper, we present a new methodology towards performing highlevel synthesis. During highlevel synthesis an algorithmic description is mapped to a structure of hardware components. In our approach, highlevel synthesis is performed via program transformations. All transformations are perform ..."
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Cited by 9 (3 self)
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In this paper, we present a new methodology towards performing highlevel synthesis. During highlevel synthesis an algorithmic description is mapped to a structure of hardware components. In our approach, highlevel synthesis is performed via program transformations. All transformations are performed within a higher order logic theorem prover thus guaranteeing correctness. Our approach is not restricted to data flow graphs but supports arbitrary computable functions, i.e. mixed control/data flow graphs. Furthermore, the treatment of algorithmic and interface descriptions is orthogonalised, allowing systematic reuse of designs.
Theorem Proving Guided Development of Formal Assertions in a ResourceConstrained Scheduler for HighLevel Synthesis
 Proceedings of International Conference on Computer Design (ICCD'98
, 1998
"... This paper presents a formal specification and a proof of correctness of the widelyused ForceDirected List Scheduling (FDLS) algorithm for resourceconstrained scheduling of data flow graphs in highlevel synthesis systems. The proof effort is conducted using a higherorder logic theorem prover ..."
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Cited by 7 (2 self)
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This paper presents a formal specification and a proof of correctness of the widelyused ForceDirected List Scheduling (FDLS) algorithm for resourceconstrained scheduling of data flow graphs in highlevel synthesis systems. The proof effort is conducted using a higherorder logic theorem prover. During the proof effort many interesting properties of the FDLS algorithm are discovered. These properties are formally stated and proved in a higherorder logic theorem proving environment. These properties constitute a detailed set of formal assertions and invariants that should hold at various steps in the FDLS algorithm. They are then inserted as programming assertions in the implementation of the FDLS algorithm in a productionstrength highlevel synthesis system. When turned on, the programming assertions (1) certify whether a specific run of the FDLS algorithm produced correct schedules and, (2) in the event of failure, help discover and isolate programming errors in the FDLS impl...
A Formal Approach to Specify and Synthesize at the System Level
 In GI Workshop Modellierung und Verifikation von Systemen
, 1999
"... In this paper, a new and formal methodology for specifying and synthesizing systems is presented. Systems are modeled as structures of concurrent processes. The way the processes communicate realizes a handshake protocol. The specification at the system level is part of our hardware description ..."
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Cited by 6 (1 self)
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In this paper, a new and formal methodology for specifying and synthesizing systems is presented. Systems are modeled as structures of concurrent processes. The way the processes communicate realizes a handshake protocol. The specification at the system level is part of our hardware description language Gropius, which ranges from the gate to the system level. Gropius was designed for a formal synthesis scenario, where synthesis is performed by applying basic mathematical rules within a theorem prover, thus guaranteeing correctness of designs implicitly.
Formally Embedding Existing High Level Synthesis Algorithms
 Correct Hardware Design and Verification Methods, number 987 in Lecture Notes in Computer Science
, 1995
"... This paper introduces a general scheme for formally embedding high level synthesis by formulating its basic steps as transformations within higher order logic. A functional representation of a data flow graph is successively refined by means of generic logical transformations. ..."
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Cited by 6 (2 self)
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This paper introduces a general scheme for formally embedding high level synthesis by formulating its basic steps as transformations within higher order logic. A functional representation of a data flow graph is successively refined by means of generic logical transformations.
On Automatic and Interactive Design of Communicating Systems
, 1995
"... This paper presents a transformational approach to the design of distributed systems where environment and concurrently running components communicate via synchronous message passing along directed channels. System specifications that combine tracebased with statebased reasoning are gradually m ..."
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Cited by 4 (1 self)
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This paper presents a transformational approach to the design of distributed systems where environment and concurrently running components communicate via synchronous message passing along directed channels. System specifications that combine tracebased with statebased reasoning are gradually modified by application of transfromation rules until occamlike programs are achieved finally. We consider interactive and automatic aspects of such a design process and illustrate our approach by sketching the development of a shared register implementation. 1
On the Effectiveness of Theorem Proving Guided Discovery of Formal Assertions for a Register Allocator in a HighLevel Synthesis System
 Proceedings of 11th Conference on Theorem Proving in Higher Or der Logics (TPHOL'98
"... . This paper presents a formal specification and a proof of correctness for the register optimization task in highlevel synthesis. A widely implemented register optimization algorithm is modeled in higherorder logic and verified in a theorem prover environment. A rich collection of correctness ..."
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Cited by 3 (3 self)
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. This paper presents a formal specification and a proof of correctness for the register optimization task in highlevel synthesis. A widely implemented register optimization algorithm is modeled in higherorder logic and verified in a theorem prover environment. A rich collection of correctness properties is systematically formulated during the theorem proving exercise. These properties constitute a detailed set of formal assertions that are identified with the invariants at various stages of the algorithm. The formal assertions are then embedded as programming assertions in the implementation of the register optimization algorithm in a productionstrength highlevel synthesis system. When turned on, the programming assertions (1) certify whether a specific run of the highlevel synthesis system produced designs with errorfree register allocation and, (2) in the event of a failure, help discover and isolate programming errors in the implementation. We present a detaile...
Formal Synthesis at the Algorithmic Level
 In: Correct Hardware Design and Veri Methods, Charme'99
, 1999
"... . In our terminology, the term "formal synthesis" stands for a synthesis process where the implementation is derived from the specification by applying elementary mathematical rules within a theorem prover. As a result the implementation is guaranteed to be correct. In this paper we introduce a new ..."
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Cited by 3 (3 self)
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. In our terminology, the term "formal synthesis" stands for a synthesis process where the implementation is derived from the specification by applying elementary mathematical rules within a theorem prover. As a result the implementation is guaranteed to be correct. In this paper we introduce a new methodology to formally derive registertransfer structures from descriptions at the algorithmic level via program transformations. Some experimental results at the end of the paper show how the runtime complexity of the synthesis process in our approach could be. 1 Introduction The synthesis of hardware systems is heading toward more and more abstract design levels. This is due to the fact that the systems are becoming more complex and so does the synthesis process for deriving them. Therefore, the correctness of hardware components has become an important matter  especially in safetycritical domains. By correctness we mean that the synthesis result (implementation) satisfies the synt...