A logic simulator can prove the correctness of a digital circuit if it can be shown that only circuits implementing the system specification will produce a particular response to a sequence of simulation commands. Three-valued modeling, where the third state X indicates a signal with unknown digital value, can greatly reduce the number of patterns that need to be simulated for complete verification. As an extreme case, an N -bit random-access memory (RAM) can be verified by simulating just O(N log N) patterns. This approach to verification is fast, requires minimal attention on the part of the user to the circuit details, and can utilize more sophisticated circuit models than other approaches to formal verification. The technique has been applied to a CMOS static RAM design using the COSMOS switch-level simulator. By simulating

Automatic Test Pattern Generation (ATPG) systems are tools for generating tests for digital circuits. Due to the complexity of very large scale integrated circuits, such systems are essential for achieving tests with high fault coverage. This thesis presents time efficient ATPG systems for combinational and sequential circuits. First, a fast, effective deterministic test generation algorithm provides a time efficient ATPG system for combinational circuits. This algorithm utilizes a new fast fault simulation algorithm, Parallel Pattern Critical Path Tracing (PPCPT). At the earlier stages of test set simulation, PPCPT takes advantage of critical path tracing, then dynamically transforms to parallel pattern single fault propagation as the simulation progresses. Further, for concurrent engineering design environments, an incremental ATPG concept is introduced. When there is a small circuit modification, incremental test generation utilizes information from tests for the original circuit to...

We prove the equivalence between the ternary circuit model and a notion of intuitionistic stabilization bounds. The results are obtained as an application of the timing interpretation of intuitionistic propositional logic presented in [12]. We show that if one takes an intensional view of the ternary model then the delays that have been abstracted away can be completely recovered. Our intensional soundness and completeness theorems imply that the extracted delays are both correct and exact; thus we have developed a framework which unifies ternary simulation and functional timing analysis. Our focus is on the combinational behaviour of gate-level circuits with feedback.

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Classical logic has so far been the logic of choice in formal hardware verification. This paper proposes the application of intuitionistic logic to the timing analysis of digital circuits. The intuitionistic setting serves two purposes. The model-theoretic properties are exploited to handle the second-order nature of bounded delays in a purely propositional setting without need to introduce explicit time and temporal operators. The proof theoretic properties are exploited to extract quantitative timing information and to reintroduce explicit time in a convenient and systematic way. We present a natural Kripke-style semantics for intuitionistic propositional logic, as a special case of a Kripke constraint model for Propositional Lax Logic [15], in which validity is validity up to stabilisation, and implication oe comes out as "boundedly gives rise to." We show that this semantics is equivalently characterised by a notion of realisability with stabilisation bounds as realisers...

We define functional abstraction as the process of deliberately ignoring the dependence of a Boolean function on a subset of its variables. Functional abstraction causes a completely specified function to become partially specified. We propose function sets as a theoretical model for partially specified functions and function intervals as a practical approximation to them. We develop an interval Boolean algebra suitable for the symbolic manipulation of function intervals and highlight the relationship between functional abstraction and universal and existential quantification. CSE-TR-255-95: Functional Abstraction and Partial Specification of Boolean Functions 1 Notational Conventions and Glossary of Symbols We will generally use lower-case symbols to denote scalar quantities and upper-case symbols to denote aggregates (vectors and sets.) Calligraphic type will denote the carriers (universal sets) of algebraic structures. Unless explicitly stated otherwise, when we speak of Boolean variables and functions we mean variables and functions in the 2-element Boolean (switching) algebra. Thus, x1, x2, …, xn refer to switching variables, f, g, h denote switching functions, X ( x1, x2, …, xn) represents a vector of switching variables, and F, G, H denote sets of switching functions.

Iwould especially like to thank Steve Levitan for his guidance and patience throughout the development of this tool.