Results 1  10
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13
Time Efficient Automatic Test Pattern Generation Systems
, 1994
"... Automatic Test Pattern Generation (ATPG) systems are tools for generating tests for digital circuits. Due to the complexity of very large scale integrated circuits, such systems are essential for achieving tests with high fault coverage. This thesis presents time efficient ATPG systems for combinati ..."
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Cited by 11 (0 self)
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Automatic Test Pattern Generation (ATPG) systems are tools for generating tests for digital circuits. Due to the complexity of very large scale integrated circuits, such systems are essential for achieving tests with high fault coverage. This thesis presents time efficient ATPG systems for combinational and sequential circuits. First, a fast, effective deterministic test generation algorithm provides a time efficient ATPG system for combinational circuits. This algorithm utilizes a new fast fault simulation algorithm, Parallel Pattern Critical Path Tracing (PPCPT). At the earlier stages of test set simulation, PPCPT takes advantage of critical path tracing, then dynamically transforms to parallel pattern single fault propagation as the simulation progresses. Further, for concurrent engineering design environments, an incremental ATPG concept is introduced. When there is a small circuit modification, incremental test generation utilizes information from tests for the original circuit to...
Formal Verification of Memory Circuits by SwitchLevel Simulation
, 1999
"... A logic simulator can prove the correctness of a digital circuit if it can be shown that only circuits implementing the system specification will produce a particular response to a sequence of simulation commands. Threevalued modeling, where the third state X indicates a signal with unknown digi ..."
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Cited by 11 (6 self)
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A logic simulator can prove the correctness of a digital circuit if it can be shown that only circuits implementing the system specification will produce a particular response to a sequence of simulation commands. Threevalued modeling, where the third state X indicates a signal with unknown digital value, can greatly reduce the number of patterns that need to be simulated for complete verification. As an extreme case, an N bit randomaccess memory (RAM) can be verified by simulating just O(N log N) patterns. This approach to verification is fast, requires minimal attention on the part of the user to the circuit details, and can utilize more sophisticated circuit models than other approaches to formal verification. The technique has been applied to a CMOS static RAM design using the COSMOS switchlevel simulator. By simulating
Ternary Simulation: A Refinement of Binary Functions or an Abstraction of RealTime Behaviour?
 PROCEEDINGS OF THE 3RD WORKSHOP ON DESIGNING CORRECT CIRCUITS (DCC96
, 1996
"... We prove the equivalence between the ternary circuit model and a notion of intuitionistic stabilization bounds. The results are obtained as an application of the timing interpretation of intuitionistic propositional logic presented in [12]. We show that if one takes an intensional view of the ternar ..."
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Cited by 9 (3 self)
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We prove the equivalence between the ternary circuit model and a notion of intuitionistic stabilization bounds. The results are obtained as an application of the timing interpretation of intuitionistic propositional logic presented in [12]. We show that if one takes an intensional view of the ternary model then the delays that have been abstracted away can be completely recovered. Our intensional soundness and completeness theorems imply that the extracted delays are both correct and exact; thus we have developed a framework which unifies ternary simulation and functional timing analysis. Our focus is on the combinational behaviour of gatelevel circuits with feedback.
A TwoState Methodology for RTL Logic Simulation
 Proc. 36th Design Automation Conf
, 1999
"... This paper describes a twostate methodology for register transfer level (RTL) logic simulation in which the use of the Xstate is completely eliminated inside ASIC designs. Examples are presented to show the gross pessimism and optimism that occurs with the X in RTL simulation. Random twostate ini ..."
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Cited by 7 (1 self)
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This paper describes a twostate methodology for register transfer level (RTL) logic simulation in which the use of the Xstate is completely eliminated inside ASIC designs. Examples are presented to show the gross pessimism and optimism that occurs with the X in RTL simulation. Random twostate initialization is offered as a way to detect and diagnose startup problems in RTL simulation. Random twostate initialization (a) is more productive than the Xstate in gatelevel simulation, and (b) provides better coverage of startup problems than Xstate in RTL simulation. Consistent random initialization is applied (a) as a way to duplicate a startup state using a slower diagnosisoriented simulator after a faster detectionoriented simulator reports the problem, and (b) to verify that the problem is corrected for that startup state after the design change intended to fix the problem. In addition to combining the earlier ideas of twostate simulation, and random initialization with consistent values across simulations, an original technique for treatment of tristate Z's arriving into a twostate model is introduced.
Timing Analysis of Combinational Circuits in Intuitionistic Propositional Logic
 Formal Methods in System Design
, 1999
"... Classical logic has so far been the logic of choice in formal hardware verification. This paper proposes the application of intuitionistic logic to the timing analysis of digital circuits. The intuitionistic setting serves two purposes. The modeltheoretic properties are exploited to handle the s ..."
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Cited by 5 (1 self)
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Classical logic has so far been the logic of choice in formal hardware verification. This paper proposes the application of intuitionistic logic to the timing analysis of digital circuits. The intuitionistic setting serves two purposes. The modeltheoretic properties are exploited to handle the secondorder nature of bounded delays in a purely propositional setting without need to introduce explicit time and temporal operators. The proof theoretic properties are exploited to extract quantitative timing information and to reintroduce explicit time in a convenient and systematic way. We present a natural Kripkestyle semantics for intuitionistic propositional logic, as a special case of a Kripke constraint model for Propositional Lax Logic [15], in which validity is validity up to stabilisation, and implication oe comes out as "boundedly gives rise to." We show that this semantics is equivalently characterised by a notion of realisability with stabilisation bounds as realisers...
Synthesis for logical initializability of synchronous finite state machines
 in Proc. of Intl. Conf. on VLSI Design, pp 7680
, 1997
"... Abstract—Logical initializability is the property of a gatelevel circuit whereby it can be driven to a unique start state when simulated by a threevalued (0, 1, ) simulator. In practice, commercial logic and fault simulators often require initialization under such a threevalued simulation model. ..."
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Abstract—Logical initializability is the property of a gatelevel circuit whereby it can be driven to a unique start state when simulated by a threevalued (0, 1, ) simulator. In practice, commercial logic and fault simulators often require initialization under such a threevalued simulation model. In this paper, the first sound and systematic synthesis method is proposed to ensure the logical initializability of synchronous finitestate machines. The method includes both state assignment and combinational logic synthesis steps. It is shown that a previous approach to synthesisforinitializability, which uses a constrained state assignment method, may produce uninitializable circuits. Here, a new state assignment method is proposed that is guaranteed correct. Furthermore, it is shown that combinational logic synthesis also has a direct impact on initializability; necessary and sufficient constraints on combinational logic synthesis are proposed to guarantee that the resulting gatelevel circuits are logically initializable. The above two synthesis steps have been incorporated into a computeraided design tool, salsify, targeted to both twolevel and multilevel implementations. Index Terms—Automatic testpattern generation (ATPG), design for testability, finitestate machines, hazards, initializability, logic simulation, logic synthesis, state assignment, synchronizing sequence, testability, testing, threevalued simulation. I.
Functional Abstraction and . . .
, 1995
"... We define functional abstraction as the process of deliberately ignoring the dependence of a Boolean function on a subset of its variables. Functional abstraction causes a completely specified function to become partially specified. We propose function sets as a theoretical model for partially speci ..."
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We define functional abstraction as the process of deliberately ignoring the dependence of a Boolean function on a subset of its variables. Functional abstraction causes a completely specified function to become partially specified. We propose function sets as a theoretical model for partially specified functions and function intervals as a practical approximation to them. We develop an interval Boolean algebra suitable for the symbolic manipulation of function intervals and highlight the relationship between functional abstraction and universal and existential quantification.
Signature
, 1991
"... Iwould especially like to thank Steve Levitan for his guidance and patience throughout the development of this tool. ..."
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Iwould especially like to thank Steve Levitan for his guidance and patience throughout the development of this tool.