A simple cascode circuit with the gate voltage of the cascode transistor being controlled by a feedback ampli #er and thus named `regulated cascode' is presented. In comparison to the standard cascode circuit the minimum output voltage is lower by about 30 to 60 # while the output conductance and the feedback capacitance are lower by about 100 times. An analytical large-signal, small-signal, and noise analysis is carried out. Some applications like current mirrors and voltage ampli#ers are discussed. Finally, experimental results con#rming the theory are presented. I. Introduction C IRCUITS that behave like a MOS transistor but feature a much higher output-impedance and a signi#- cantly lower feedback capacitance are an important prerequisite for the design of high-performance analog circuits. If such a circuit is used in a tail current-source of a di#erential stage, the common-mode and power-supply rejection ratios are improved. If it is used in a voltage ampli#er, a large dc gain-...

A continuous-time common-mode feedback circuit (CMFB) is presented. A two-stage high-gain architecture is used to minimize the offset of the common-mode voltage. A special compensation scheme enables this circuit to be used in high-impedance current-mode systems without a stability problem. Simulation and testing results show the superior performance of this circuit. It is proven to be an ideal common-mode feedback circuit for systems which require an accurate and stable commonmode voltage. This circuit has been implemented in a continuous-time switched-current modulator with a 2 m CMOS process. With a 50MHz clock, the modulator has achieved a 60dB dynamic range in a 1MHz bandwidth. 1.

The settling behavior and power consumption of dynamic opamps are considered. The dynamic opamp is compared with a class A opamp for different clock frequencies. A single pole model in a closed loop configuration is used to estimate slewing and settling behavior. SPICE simulation results agree with theoretical predictions. It is shown that for the same power consumption dynamic opamps settle much faster than class A opamps. Dynamic opamps are particularly well suited for ultra low power switched-capacitor designs.

Abstract- In this paper we discuss the design of a low-voltage (1.5V), continuous-time, biquadratic CMOS filter based on Dynamic Gate Biasing (DGB). We begin by discussing the filter’s structure and its tuning mechanism. The filter uses transconductance-C cells and implements low-pass, bandpass and highpass transfer functions. The transconductances are tuned using the gate voltages of MOSFETs operating in the triode region. We review the principle of DGB, and discuss the design of the charge pump based on the filter’s performance and tunability requirements. Circuit details of the filter elements and the charge pump are presented along with SPICE simulation results of the overall filter. I.

Oversampled Analog-to-Digital conversion has been demonstrated to be an effective technique for high resolution analog-to-digital (A/D) conversion that is tolerant to process imperfections. The area and power budget of conventionally designed oversampled analog-to-digital converters has precluded their application from areas where a large number of low frequency signals need to be converted simultaneously. A new oversampled A/D design methodology is proposed to cut the area and power budget per channel of an oversampled analog-todigital converter. The design and implementation of a 16-channel oversampled analog-to-digital converter is presented which can be used as the core of the multichannel data acquisition system. The prototype achieved 80 dB of signal-to-noise-plus-distortion over 1 kHz,-80 dB of crosstalk and used less than 20 mW of power excluding clock generation.

We present a functional approach, based on the ACL2 logic, for the specification of system on a chip communication architectures.

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... or its variations. Also included in the filter implementation is a linear programming approach to optimize the dynamic range, under the constraint of a fixed capacitor area that is assumed to be the dominant factor in the total chip area.