The growing packing density and power consumption of VLSI circuits have made thermal effects one of the most important concerns of VLSI designers. The increasing variability of key process parameters in nanometer CMOS technologies has resulted in larger impact of the substrate and metal line temperatures on the reliability and performance of the devices and interconnections. Recent data shows that more than 50 % of all IC failures are related to thermal issues. This article presents a brief discussion of key sources of power dissipation and their temperature relation in CMOS VLSI circuits, and techniques for full-chip temperature calculation with especial attention to its implications on the design of highperformance, low power VLSI circuits. The article is concluded with an overview of techniques to improve the full-chip thermal integrity by means of off-chip vs. on-chip and static vs. adaptive methods.

Abstract—In this paper, we present an efficient method to solve the coupled circuit-field problem, by first transforming the partial differential equations (PDEs) governing the field problem into a simple one–dimensional (1-D) equivalent circuit system, which is then combined with the circuit part of the overall coupled problem. This transformation relies on the generalized Falk algorithm, which transforms the coordinates in any complex system of linear first-order ordinary differential equations (ODEs) or second-order undamped ODEs, resulting from the discretization of field PDEs, into guaranteed stable-and-passive 1-D equivalent circuit system. The generalized Falk algorithm, having a faster transformation time compared with the traditional Lanczos-type methods, transforms a general finite-element system represented by possibly a system of full matrices—capacitance and conductance matrices in heat problems, or mass and stiffness matrices in structural dynamics and electromagnetics—into an identity capacitance (mass) matrix and a tridiagonal conductance (stiffness) matrix. We also discuss issues related to the stability and the loss of orthogonality of the proposed algorithm. In circuit simulation, the generalized Falk algorithm does not produce unstable positive poles, and is thus more stable than the widely used Lanczos-type methods. The stability and passivity of the resulting 1-D equivalent circuit network are guaranteed since all transformed matrices remain positive definite. The resulting 1-D equivalent circuit system contains only resistors, capacitors, inductors, and current sources. The generalized Falk algorithm offers an extremely simple and convenient way to incorporate field problems into circuit simulators to efficiently solve coupled circuit-field problems. Numerical examples show a significant reduction of simulation time compared to the solution without using the proposed transformation.

An electrothermal model for a power electronic module is presented. The model is developed by representing the internal thermal behavior of the module as a RC network using an electrical circuit equivalent for the thermal heat conduction equation in one dimension. The physical characteristics of the module, like thermal properties of its constituents and all its dimensions, are used to subdivide its structure into a finite number of thermal components or nodes. To validate the model, two experiments were made: a train of high-power pulses was applied to obtain a fast-transient response of the innermost layers close to the semiconductor junctions, and a constant low-power level was applied to obtain a slow-transient response of different points located throughout the module plus its heat dissipation elements. Simulations performed with the module model showed an acceptable agreement with the acquired experimental measurements. i RESUMEN Un modelo electrotermal para un módulo de electrónica de potencia es

A new algorithm has been developed for the layout based direct electro-thermal simulation of integrated circuits. The advantage of the direct electro-thermal simulation over simulator coupling is, that very fast changes can also be considered, the drawback is that the thermal nodes are added to the number of nodes of the network to be simulated. The novelties of our method are the modeling and the solution of the thermal structure. This paper presents the algorithm of the time constant spectrum based FOSTER chain matrix thermal modeling, and the new algorithm of the coupled electro-thermal solution, where parts of the network, which represent the thermal behavior, are not computed in all steps of the iteration. This speeded up algorithm works both in the time-, and in the frequency domain. A simulation example demonstrates a typical application: the prediction of how the layout arrangement and the packaging of an analogue integrated circuit influence the electrical parameters.

This dissertation presents a multi-faceted effort at developing standard System Design Language based tools that allow designers to the model power and thermal behavior of SoCs, including heterogeneous SoCs that include non-digital components. The research contributions made in this dissertation include: • SystemC-based power/performance co-simulation for the Intel XScale microprocessor. We performed detailed characterization of the power dissipation patterns of a variety of system components and used these results to build detailed power models, including a highly accurate, validated instruction-level power model of the XScale processor. We also proposed a scalable, efficient and validated methodology for incorporating fast, accurate power modeling capabilities into system description languages such as SystemC. This was validated against physical measurements of hardware power dissipation. • Modeling the behavior of non-digital SoC components within standard System Design Languages. We presented an approach for modeling the functionality, performance, power, and thermal behavior of a complex class of non-digitalcomponents — MEMS microhotplate-based gas sensors — within a SystemC