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Stable and efficient reduction of large, multiport RC networks by pole analysis via congruence transformations,” submitted to
 IEEE Trans. ComputerAided Design
"... Abstract — A novel technique is presented which employs Pole Analysis via Congruence Transformations (PACT) to reduce RC networks in a wellconditioned manner. Pole analysis is shown to be more efficient than Padé approximations when the number of network ports is large, and congruence transformati ..."
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Cited by 43 (0 self)
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Abstract — A novel technique is presented which employs Pole Analysis via Congruence Transformations (PACT) to reduce RC networks in a wellconditioned manner. Pole analysis is shown to be more efficient than Padé approximations when the number of network ports is large, and congruence transformations preserve the passivity (and thus absolute stability) of the networks. Networks are represented by admittance matrices throughout the analysis, and this representation simplifies interfacing the reduced networks with circuit simulators as well as facilitates realization of the reduced networks using RC elements. A prototype SPICEin, SPICEout, network reduction CAD tool called RCFIT is detailed, and examples are presented which demonstrate the accuracy and efficiency of the PACT algorithm. 1.
Hotspot: a dynamic compact thermal model at the processor architecture level. Microelectronics Journal: Circuit and Systems
, 2003
"... This paper describes a thermalmodeling approach that is easy to use and computationally efficient for modeling thermal effects and thermalmanagement techniques at the processor architecture level. Our approach is based on modeling thermal behavior of the microprocessor die and its package as a ci ..."
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Cited by 21 (6 self)
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This paper describes a thermalmodeling approach that is easy to use and computationally efficient for modeling thermal effects and thermalmanagement techniques at the processor architecture level. Our approach is based on modeling thermal behavior of the microprocessor die and its package as a circuit of thermal resistances and capacitances that correspond to functional blocks at the architecture level. This yields a simple compact model, yet heat dissipation within all major functional blocks and the heat flow among blocks and through the package are accounted for. The model is parameterized, boundary and initialconditions independent, and is derived by a structure assembly approach. The architecture community has demonstrated growing interest in thermal management, but currently lacks a way to model onchip temperatures in a tractable way. Our model can be used for initial exploration of the design space at the architecture level. The model can easily be integrated into popular power/performance simulators, can be used to determine how thermal stress is correlated to the architecture, and how architecturelevel design decisions influence thermal behavior and related effects.
ElectroThermal Circuit Simulation Using Simulator Coupling
 IEEE Trans. Very Large Scale Integration Systems
, 1997
"... Abstract The paper presents a methodology for simulating the static and dynamic performance of integrated circuits in the presence of electrothermal interactions on the integrated circuit die. The technique is based on the coupling of a finite element method (FEM) program with a circuit simulator. ..."
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Cited by 13 (1 self)
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Abstract The paper presents a methodology for simulating the static and dynamic performance of integrated circuits in the presence of electrothermal interactions on the integrated circuit die. The technique is based on the coupling of a finite element method (FEM) program with a circuit simulator. In difference to other known simulator couplings a time step algorithm is used. Its implementation into simulation tools is described. The thermal modeling of the die/package structure and the extended modeling of the electronic circuit is discussed. Simulation results which indicate the capabilities of the methodology for electrothermal simulation are compared to experimental results. Index Terms Analog modeling with behavioral languages, circuit simulation, electrothermal circuit simulation, finite element simulation, simulator coupling, thermal modeling. I.
A.Poppe, “A fast algorithm for the layout based electrothermal simulation” DATE’03 [link
 in Proc. Design, Automation and Test in Europe Conf
"... A new algorithm has been developed for the layout based direct electrothermal simulation of integrated circuits. The advantage of the direct electrothermal simulation over simulator coupling is, that very fast changes can also be considered, the drawback is that the thermal nodes are added to the ..."
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A new algorithm has been developed for the layout based direct electrothermal simulation of integrated circuits. The advantage of the direct electrothermal simulation over simulator coupling is, that very fast changes can also be considered, the drawback is that the thermal nodes are added to the number of nodes of the network to be simulated. The novelties of our method are the modeling and the solution of the thermal structure. This paper presents the algorithm of the time constant spectrum based FOSTER chain matrix thermal modeling, and the new algorithm of the coupled electrothermal solution, where parts of the network, which represent the thermal behavior, are not computed in all steps of the iteration. This speeded up algorithm works both in the time, and in the frequency domain. A simulation example demonstrates a typical application: the prediction of how the layout arrangement and the packaging of an analogue integrated circuit influence the electrical parameters. 1.
SemiAnalytical Techniques for Substrate Characterization
 in the Design of MixedSignal ICs”, ICCAD
, 1996
"... A number of methods are presented for highly efficient calculation of substrate current transport. A threedimensionalGreen’s Function based substrate representation, in combination with the use of the Fast Fourier Transform, significantly speeds up the computation of sensitivities with respect to a ..."
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A number of methods are presented for highly efficient calculation of substrate current transport. A threedimensionalGreen’s Function based substrate representation, in combination with the use of the Fast Fourier Transform, significantly speeds up the computation of sensitivities with respect to all parameters associated with a given architecture. Substrate sensitivity analysis is used in a number of physical optimization tools, such as placement and trend analysis for the estimation of the impact of technology migration and/or layout redesign. 1
IEEE TRANSACTIONS ON COMPONENTS, PACKAGING, AND MANUFACTURING TECHNOLOGY 1 Interconnection of Subsystem ReducedOrder Models in the ElectroThermal Analysis of Large Systems
"... Abstract—Heat conduction in an electronic device is commonly modeled as a discretized thermal system (eg, finite element or finite difference models) that typically uses large matrices for solving complex problems. The large size of electronicsystem heat transfer models can be reduced using model r ..."
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Abstract—Heat conduction in an electronic device is commonly modeled as a discretized thermal system (eg, finite element or finite difference models) that typically uses large matrices for solving complex problems. The large size of electronicsystem heat transfer models can be reduced using model reduction methods and the resulting reducedorder models can yield accurate results with far less computational costs. Electronic devices are typically composed of components, like chips, printed circuit boards, and heat sinks that are coupled together. There are two ways of creating reducedorder models for devices that have many coupled components. The first way is to create a single reducedorder model of the entire device. The second way is to interconnect reducedorder models of the components that constitute the device. The second choice (which we call the “reduce then interconnect ” approach) allows the heat transfer specialist to perform quick simulations of different architectures of the device by using a library of reducedorder models of the different components that make up the device. However, interconnecting reducedorder models in a straightforward manner can result in unstable behavior. The purpose of this paper is twofold: creating reducedorder models of the components using a Krylov subspace algorithm and interconnecting the reducedorder models in a stable manner using concepts from control theory. In this paper we explain the logic behind the “reduce then interconnect ” approach, formulate a controltheoretic method for it, and finally exhibit the whole process numerically, by applying it to an example heat conduction problem. Index Terms—Electrothermal analysis, heat conduction, interconnecting reducedorder models, compact modeling, Krylov model reduction. I.
unknown title
"... The microsystem design process is characterized by interdisciplinary approaches and close interactions between different domains. A methodology for simulating the performance of complex microsystems using simulator coupling is presented. The technique is based on the coupling of the FEM program ..."
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The microsystem design process is characterized by interdisciplinary approaches and close interactions between different domains. A methodology for simulating the performance of complex microsystems using simulator coupling is presented. The technique is based on the coupling of the FEM program ANSYS with the circuit and system simulator SABER. In difference to other known simulator couplings a time step algorithm is employed. Its methodology is reported and the implementation into simulation tools is explained. The system simulations of an accelerometer sensor system as well as the simulation of a thermal interaction in integrated circuits prove the suitability of the coupling. Finally, simulation results are discussed and advantages of the implemented coupling are concluded. 1
A METHODOLOGY FOR MEMORY CHIP STRESS LEVELS PREDICTION Approved by:
, 2005
"... The reliability of an electronic component plays an important role in proper functioning of the electronic devices. The manufacturer tests electronic components before they are used by end users. Still at times electronic devices fail due to undue stresses existing inside the microelectronic compone ..."
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The reliability of an electronic component plays an important role in proper functioning of the electronic devices. The manufacturer tests electronic components before they are used by end users. Still at times electronic devices fail due to undue stresses existing inside the microelectronic components such as memory chips, microcontrollers, resistors etc. The stresses can be caused by variation in the operating voltage, variation in the usage frequency of the particular chip and other factors. This variation leads to variation in chip temperature, which can be made evident from thermal profiles of these chips. In this thesis, effort was made to study two different kind of stress existing in the electronic board, namely signal stress based on variation in duty cycle/frequency of chip usage and the voltage stress. Memory chips were tested using these stresses causing change in heating rates, which were captured by infrared camera. This data was then extracted and plotted to obtain different curves for the heating rate. The same experiment was done time and again for a large number of chips to get heating rate data. This data consisting of average heating rate for large number of chips was used
Director of Graduate Studies
, 2004
"... This work presents a reduced mathematical model using a practical numerical formulation of the thermal behavior of an Integrated Power Electronics Module (IPEM). This model is based on the expanded Lumped Thermal Capacitance Method (LTCM), in which the number of variables involved in the analysis of ..."
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This work presents a reduced mathematical model using a practical numerical formulation of the thermal behavior of an Integrated Power Electronics Module (IPEM). This model is based on the expanded Lumped Thermal Capacitance Method (LTCM), in which the number of variables involved in the analysis of heat transfer is reduced only to time. By applying this procedure a simple, nonspatial, but highly nonlinear model is obtained. Transient results of the model were validated using FLOTHERM 3.1 TM, a thermal analysis software tool. Two experimental setup, for low and highspeed thermal response, were developed. Comparisons between thermal model results and experimental data are also presented to demonstrate the need to obtain the electrical performance and to make the electrothermal coupling. The development of this model presents an alternative to reduce the complexity level developed in commercial multidimensional and transient thermal analysis software tools. i RESUMEN