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On the Modeling and Verification of a Telecom System Block Using MDGs
, 2000
"... Abstract. In this report, we investigate the ability of MDGs (Multiway Decision Graphs) to carry out a verification process of a large industrial Telecom hardware which is commercialized by PMCSierra Inc. Until recently, the Cambridge Fairisle ATM switch fabric with 4200 equivalent gates was the la ..."
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Abstract. In this report, we investigate the ability of MDGs (Multiway Decision Graphs) to carry out a verification process of a large industrial Telecom hardware which is commercialized by PMCSierra Inc. Until recently, the Cambridge Fairisle ATM switch fabric with 4200 equivalent gates was the largest industrial like design verified with the MDG tools. The design we consider in this study is a Telecom System Block (TSB), called RASE, containing 11400 equivalent gates. For the formal verification, we adopted a hierarchical proof methodology to handle the complexity of the design. We then carried out MDG based equivalence checking as well as model checking. To measure the performance of the MDG verification, we also conducted the verification of the same TSB with Cadence FormalCheck. The experimental results showed that in some state variables and uninterpreted function symbols rather than simply a Boolean modeling as in FormalCheck. 1.
Formal Verification of ASM Designs Using the MDG Tool
 Software Engineering and Formal Methods, IEEE Computer Society
, 2003
"... State Machine) is a state based language for describing transition systems. MDG (Multiway Decision Graphs) provides symbolic representation of transition systems with support of abstract sorts and functions. We implemented a transformation tool that automatically generates MDG models from ASM specif ..."
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State Machine) is a state based language for describing transition systems. MDG (Multiway Decision Graphs) provides symbolic representation of transition systems with support of abstract sorts and functions. We implemented a transformation tool that automatically generates MDG models from ASM specifications, then formal verification techniques provided by the MDG tool, such as model checking or equivalence checking, can be applied on the generated models. We support this work with a case study of an Island Tunnel Controller, which behavior and structure were specified in ASM then using our ASMMDG tool successfully verified within the MDG tool.
Formal Verification of a SONET Telecom System Block
, 2002
"... In this paper, we describe the formal verification of an industrial hardware design from PMCSierra, Inc. The design under investigation is a Telecom System Block which processes a portion of the SONET (Synchronous Optical Network) line overhead of a received data stream. We adopted a hierarchical m ..."
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In this paper, we describe the formal verification of an industrial hardware design from PMCSierra, Inc. The design under investigation is a Telecom System Block which processes a portion of the SONET (Synchronous Optical Network) line overhead of a received data stream. We adopted a hierarchical modeling and verification approach which follows the natural design hierarchy. The formal specification and verification have been carried out based on MDGs (Multiway Decision Graphs), a new decision diagram subsuming the traditional binary decision diagrams and allowing abstract data and functions. The verification has been performed using both model checking and equivalence checking. To measure the performance...
A High Level Reachability Analysis using Multiway Decision Graph in the HOL Theorem Prover
"... Abstract. In this paper, we provide all the necessary infrastructure to define a high level states exploration approach within the HOL theorem prover. While related work has tackled the same problem by representing primitive BDD operations as inference rules added to the core of the theorem prover, ..."
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Abstract. In this paper, we provide all the necessary infrastructure to define a high level states exploration approach within the HOL theorem prover. While related work has tackled the same problem by representing primitive BDD operations as inference rules added to the core of the theorem prover, we have based our approach on the Multiway Decision Graphs (MDGs). We define canonic MDGs as wellformed directed formulae in HOL. Then, we formalize the basic MDG operations following a deep embedding approach and we derive the correctness proof for each operation. Finally, a high level reachability analysis is implemented as a tactic that uses our MDG theory within HOL. 1
High Level Reduction Technique for Multiway Decision Graphs Based Model Checking
"... Multiway Decision Graphs (MDGs) represent and manipulate a subset of firstorder logic formulae suitable for model checking of large data path circuits. Due to the presence of abstract variables, existing reduction algorithms that is defined on symbolic model checking with BDD cannot be used with MD ..."
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Multiway Decision Graphs (MDGs) represent and manipulate a subset of firstorder logic formulae suitable for model checking of large data path circuits. Due to the presence of abstract variables, existing reduction algorithms that is defined on symbolic model checking with BDD cannot be used with MDG. In this paper we propose a technique to construct a reduced MDG model for circuits described at algorithmic level in VHDL. The simplified model can be obtained using a high level symbolic simulator called TheoSim, and by running an appropriate symbolic simulation patterns. Then, the actual proof of a temporal MDG formula will be generated. We support our reduction technique by experimental results executed on benchmark properties. Keywords: Modelchecking, Symbolic Simulation, Behavioral Models 1.
FirstOrder LTL Model Checking Using Mdgs
 Proc. Int’l Symp. Automated Technology for Verification and Analysis
, 2004
"... Abstract. In this paper, we describe a firstorder linear time temporal logic (LTL) model checker based on multiway decision graphs (MDG). We developed a firstorder temporal language, L ..."
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Abstract. In this paper, we describe a firstorder linear time temporal logic (LTL) model checker based on multiway decision graphs (MDG). We developed a firstorder temporal language, L
Integrating SAT with MDG for Efficient Invariant Checking
, 2010
"... This is to certify that the thesis prepared ..."
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, Soene Tahar
"... cation Abstract. We describe a hybrid formal hardware verication tool that links the HOL interactive proof system and the MDG automated hardware verication tool. It supports a hierarchical verication approach that mirrors the hierarchical structure of designs. We obtain advantages of both vericat ..."
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cation Abstract. We describe a hybrid formal hardware verication tool that links the HOL interactive proof system and the MDG automated hardware verication tool. It supports a hierarchical verication approach that mirrors the hierarchical structure of designs. We obtain advantages of both verication paradigms. We illustrate its use by considering a component of a communications chip. Verication with the hybrid tool is signicantly faster and more tractable than using either tool alone. 1
Block Using MDGs
, 2001
"... Simulationbased verification cannot uncover all errors in an implementation because only a small fraction of all possible cases can be considered. Formal verification is a different technique that can alleviate this problem. Because the correctness of a formally verified design implicitly involves ..."
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Simulationbased verification cannot uncover all errors in an implementation because only a small fraction of all possible cases can be considered. Formal verification is a different technique that can alleviate this problem. Because the correctness of a formally verified design implicitly involves all cases regardless of the input values. This thesis demonstrates the effectiveness of Multiway Decision Graphs (MDG) to carry out the formal verification of an industrial Telecom hardware which is commercialized by PMCSierra Inc. To handle the complexity of the design, we adopted a hierarchical proof methodology as well as a number of model abstraction and reduction techniques. Based on the hierarchy of the design, we followed a hierarchical approach for the equivalence checking of the TSB. We first verified that the RTL implementation of each module complies with the specification of its behavioral model. We also succeeded to verify the full RTL implementation of the TSB against its top level specification. Besides equivalence checking, we furthermore applied model checking to ascertain that both the specification and the implementation of the TSB satisfy some specific characteristics of the system. To measure the performance of the MDG verification, we also conducted the