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Continuoustime feedback in floatinggate MOS circuits
 IEEE Trans. Circuits Syst
, 2001
"... Abstract—We present the negative and positivefeedback circuit configurations of continuoustime floatinggate MOS circuits. We start by reviewing the dynamics of our pFET and nFET singletransistor synapses. We present the range of possible stabilizing and destabilizing types of feedback in circui ..."
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Cited by 22 (7 self)
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Abstract—We present the negative and positivefeedback circuit configurations of continuoustime floatinggate MOS circuits. We start by reviewing the dynamics of our pFET and nFET singletransistor synapses. We present the range of possible stabilizing and destabilizing types of feedback in circuits with one floatinggate synapse, including data from nFET and pFET synapses. We then show examples of competitive and cooperative behavior in multiplesynapse circuits. We present experimental data from circuits fabricated in the 2 m nwell CMOS process available through MOSIS. We see similar experimental effects in 1.2 and 0.5 m processes. Index Terms—Continuous floatinggate programming, electron tunneling, floatinggate circuits, floatinggate dynamics, hotelectron injection. I.
Analog VLSIbased Modeling of the Primate Oculomotor System
, 1997
"... One way to understand a neurobiological system is by building a functional model that replicates its behavior in realtime using similar constraints. Analog Very Large Scale Integrated (VLSI) electronic circuit technology provides such an enabling technology. We here describe a neuromorphic syst ..."
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Cited by 16 (0 self)
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One way to understand a neurobiological system is by building a functional model that replicates its behavior in realtime using similar constraints. Analog Very Large Scale Integrated (VLSI) electronic circuit technology provides such an enabling technology. We here describe a neuromorphic system that is part of a longterm effort to understand the primate oculomotor system. It requires both fast sensory processing as well as fast motor control to interact with the world. A onedimensional hardware model of the primate eye has been built which simulates the physical dynamics of the biological system. It is driven by analog VLSI circuits mimicking the brainstem and cortical circuits that control eye movements. Our oculomotor plant demonstrates both smooth pursuit movements, driven by a retinal velocity error signal, as well as saccadic eye movements, controlled by retinal position error, and can reproduce behavioral, stimulation, lesion, and adaptation experiments performed on primates.
Analysis, Synthesis, And Implementation Of Networks Of MultipleInput Translinear Elements
, 1997
"... At the time of its invention in the seventeenth century, the logarithmic slide rule literally revolutionized the way calculation was done. From then until the advent of the pocket calculator, this analog computational device was widely used to perform multiplications and divisions, to raise numbers ..."
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Cited by 11 (5 self)
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At the time of its invention in the seventeenth century, the logarithmic slide rule literally revolutionized the way calculation was done. From then until the advent of the pocket calculator, this analog computational device was widely used to perform multiplications and divisions, to raise numbers to fixed powers and extract fixed roots of numbers. Today, the slide rule may be gone, but it is not forgotten. In this thesis, I present a class of simple translinear network circuits which essentially function as electronic slide rules, accurately computing products, quotients, powers, and roots. I describe two different analysis procedures that allow us to determine the steadystate relationship between input and output currents. I also describe systematic techniques for synthesizing such circuits whereby we can produce a circuit whose steadystate transfer characteristics embody some desired productofpowerlaw relationship between input and output currents. These circuits are made from...
Onchip compensation of devicemismatch effects in analog VLSI neural networks
 Advances in Neural Information Processing Systems
, 2004
"... Device mismatch in VLSI degrades the accuracy of analog arithmetic circuits and lowers the learning performance of largescale neural networks implemented in this technology. We show compact, lowpower onchip calibration techniques that compensate for device mismatch. Our techniques enable largesc ..."
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Cited by 7 (1 self)
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Device mismatch in VLSI degrades the accuracy of analog arithmetic circuits and lowers the learning performance of largescale neural networks implemented in this technology. We show compact, lowpower onchip calibration techniques that compensate for device mismatch. Our techniques enable largescale analog VLSI neural networks with learning performance on the order of 10 bits. We demonstrate our techniques on a 64synapse linear perceptron learning with the LeastMeanSquares (LMS) algorithm, and fabricated in a 0.35µm CMOS process. 1
Competitive Learning With FloatingGate Circuits
 IEEE TRANSACTIONS ON NEURAL NETWORKS
, 2002
"... Competitive learning is a general technique for training clustering and classification networks. We have developed an 11transistor silicon circuit, that we term an automaximizing bump circuit, that uses silicon physics to naturally implement a similarity computation, local adaptation, simultaneous ..."
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Cited by 6 (1 self)
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Competitive learning is a general technique for training clustering and classification networks. We have developed an 11transistor silicon circuit, that we term an automaximizing bump circuit, that uses silicon physics to naturally implement a similarity computation, local adaptation, simultaneous adaptation and computation and nonvolatile storage. This circuit is an ideal building block for constructing competitivelearning networks. We illustrate the adaptive nature of the automaximizing bump in two ways. First, we demonstrate a silicon competitivelearning circuit that clusters onedimensional (1D) data. We then illustrate a general architecture based on the automaximizing bump circuit; we show the effectiveness of this architecture, via software simulation, on a general clustering task. We corroborate our analysis with experimental data from circuits fabricated in a 0.35µm CMOS process.
A MixedSignal Approach to HighPerformance, LowPower Linear Filters
 IEEE Journal of SolidState Circuits
, 2001
"... ..."
A 19.2 GOPS mixedsignal filter with floatinggate adaptation
 IEEE JSSC
, 2004
"... Abstract⎯We have built a 48tap, mixedsignal adaptive FIR filter with 8bit digital input and an analog output with 10 bits of resolution. The filter stores its tap weights in nonvolatile analog memory cells using synapse transistors, and adapts using the LeastMeanSquare (LMS) algorithm. We run t ..."
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Cited by 4 (2 self)
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Abstract⎯We have built a 48tap, mixedsignal adaptive FIR filter with 8bit digital input and an analog output with 10 bits of resolution. The filter stores its tap weights in nonvolatile analog memory cells using synapse transistors, and adapts using the LeastMeanSquare (LMS) algorithm. We run the input through a digital tapped delay line, multiply the digital words with the analog tap weights using mixedsignal multipliers, and adapt the tap coefficients using pulsebased feedback. The accuracy of the weight updates exceeds 13 bits. The total die area is 2.6mm 2 in a 0.35µm CMOS process. The filter delivers a performance of 19.2GOPS at 200MHz, and consumes 20mW providing a 6mA differential output current. Index Terms⎯Adaptive signal processing, FIR filter, mixedsignal VLSI, floatinggate MOSFET.
A floatinggate trimmable highresolution DAC
 in standard 0.25µm CMOS,” Proc. IEEE Nonvolatile Semiconductor Memory Workshop
, 2001
"... We have built a 14bit digitaltoanalog converter (DAC) in a standard 0.25µm digital CMOS process. We use analog values stored on floatinggate pchannel MOSFETs to trim the DAC linearity. Because the storage is nonvolatile, we eliminate the need for continuous trimming. Our design has 6 untrimmabl ..."
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Cited by 4 (3 self)
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We have built a 14bit digitaltoanalog converter (DAC) in a standard 0.25µm digital CMOS process. We use analog values stored on floatinggate pchannel MOSFETs to trim the DAC linearity. Because the storage is nonvolatile, we eliminate the need for continuous trimming. Our design has 6 untrimmable LSBs and 8 trimmable MSBs. The pretrim differential and integral nonlinearity (DNL and INL) exceeded 140 and 200 LSBs, respectively; the posttrim DNL and INL are less than 2 LSBs. We were able to trim the 8 MSBs to 0.5 LSB linearity; the 2 LSB error is due to an untrimmable bit. Because our DAC does not require continuous trimming, nor lasertrimmable resistors, it occupies only 0.17 mm2 of die area and dissipates 11 mW at 100 MHz with a –10 dBm differential output.
A FourQuadrant FloatingGate Synapse
, 1998
"... We present a new type of pFET synapse; by degenerating the source, the oxide currents provide stabilizing feedback to the oating gate and to the drain. We present experimental measurements from a oatinggate synapse that simultaniously computes fourquadrant products of its input and weight values, ..."
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Cited by 4 (2 self)
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We present a new type of pFET synapse; by degenerating the source, the oxide currents provide stabilizing feedback to the oating gate and to the drain. We present experimental measurements from a oatinggate synapse that simultaniously computes fourquadrant products of its input and weight values, and computes a fourquadrant correlation, typical of hebbian and backpropagation learning rules, between the input and drain voltages. Our fourquadrant synapse is built from two sourcedegenerated pFET synapses; by adding weak exponential feedback to the source of a oatinggate pFET synapse, we obtain a oatinggate synapse with unique dynamical properties. This fourquadrant synapse can become the fundamental building block of many continuoustime neuralnetwork learning algorithms.
Prospects for building cortexscale CMOL/CMOS circuits: a design space exploration
 In Proceedings of the 27th Norchip conference, NORCHIP2009
, 2009
"... Abstract—In this paper, we briefly present a hardware design space exploration methodology to investigate various architectures/designs, and their relative performance/price tradeoffs. Using this methodology, we investigate CMOS and hybrid nanoscale (CMOL) based digital and mixedsignal circuits th ..."
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Abstract—In this paper, we briefly present a hardware design space exploration methodology to investigate various architectures/designs, and their relative performance/price tradeoffs. Using this methodology, we investigate CMOS and hybrid nanoscale (CMOL) based digital and mixedsignal circuits that implement Bayesian Memory (a simplified computational model based on George and Hawkins ’ model of the visual cortex, and Pearl’s belief propagation), and for a cortexscale spiking neural model. We then present the results of the hardware design space exploration, for implementing largescale neuro/cortex inspired systems, and provide ballpark performance/price and scaling estimates for the same. These results provide some insight into the prospects for building largescale Bayesian Inference engines, and neuromorphic networks using emerging nanoelectronics and/or nanogrid circuit structures. In general, the study of such hypothetical architectures will help guide research trends in intelligent computing (including neuro/cognitive systems), and the use of radical new device and circuit technology in these systems. KeywordsVirtualization, timemultiplexing, spiking neuron, processing node, Bayesian memory, Pearl’s belief propagation,