We present the negative- and positive-feedback circuit congurations of continuous-time oating-gate MOS circuits. We start by reviewing the dynamics of our pFET and nFET single-transistor synapses. We present the range of possible stabilizing and destabilizing types of feedback in circuits with one oating-gate synapse, including data from nFET and pFET synapses. We then show examples of competitive and cooperative behavior in multiple-synapse circuits. We present experimental data from circuits fabricated in the 2 mnwell Orbit CMOS process available through MOSIS. One of our fundamental requirements of a silicon synapse [1-3] is that the synapse locally implements a learning rule for modifying the weight on the oating gate; in our case, the form of this rule depends on how various error signals

One way to understand a neurobiological system is by building a functional model that replicates its behavior in real-time using similar constraints. Analog Very Large Scale Integrated (VLSI) electronic circuit technology provides such an enabling technology. We here describe a neuromorphic system that is part of a long-term effort to understand the primate oculomotor system. It requires both fast sensory processing as well as fast motor control to interact with the world. A one-dimensional hardware model of the primate eye has been built which simulates the physical dynamics of the biological system. It is driven by analog VLSI circuits mimicking the brainstem and cortical circuits that control eye movements. Our oculomotor plant demonstrates both smooth pursuit movements, driven by a retinal velocity error signal, as well as saccadic eye movements, controlled by retinal position error, and can reproduce behavioral, stimulation, lesion, and adaptation experiments performed on primates.

At the time of its invention in the seventeenth century, the logarithmic slide rule literally revolutionized the way calculation was done. From then until the advent of the pocket calculator, this analog computational device was widely used to perform multiplications and divisions, to raise numbers to fixed powers and extract fixed roots of numbers. Today, the slide rule may be gone, but it is not forgotten. In this thesis, I present a class of simple translinear network circuits which essentially function as electronic slide rules, accurately computing products, quotients, powers, and roots. I describe two different analysis procedures that allow us to determine the steady-state relationship between input and output currents. I also describe systematic techniques for synthesizing such circuits whereby we can produce a circuit whose steady-state transfer characteristics embody some desired product-of-power-law relationship between input and output currents. These circuits are made from...

Device mismatch in VLSI degrades the accuracy of analog arithmetic circuits and lowers the learning performance of large-scale neural networks implemented in this technology. We show compact, low-power on-chip calibration techniques that compensate for device mismatch. Our techniques enable large-scale analog VLSI neural networks with learning performance on the order of 10 bits. We demonstrate our techniques on a 64-synapse linear perceptron learning with the Least-Mean-Squares (LMS) algorithm, and fabricated in a 0.35µm CMOS process. 1

We present a new approach to the design of high-performance low-power linear filters. We use p-channel synapse transistors as analog memory cells, and mixed-signal circuits for fast low-power arithmetic. To demonstrate the effectiveness of our approach, we have built a 16-tap 7-b 200-MHz mixed-signal finite-impulse response (FIR) filter that consumes 3 mW at 3.3 V. The filter uses synapse pFETs to store the analog tap coefficients, electron tunneling and hot-electron injection to modify the coefficient values, digital registers for the delay line, and multiplying digital-to-analog converters to multiply the digital delay-line values with the analog tap coefficients. The measured maximum clock speed is 225 MHz; the measured tap-multiplier resolution is 7 b at 200 MHz. The total die area is 0.13 mm². We can readily scale our design to longer delay lines.

Competitive learning is a general technique for training clustering and classification networks. We have developed an 11-transistor silicon circuit, that we term an automaximizing bump circuit, that uses silicon physics to naturally implement a similarity computation, local adaptation, simultaneous adaptation and computation and nonvolatile storage. This circuit is an ideal building block for constructing competitive-learning networks. We illustrate the adaptive nature of the automaximizing bump in two ways. First, we demonstrate a silicon competitive-learning circuit that clusters one-dimensional (1-D) data. We then illustrate a general architecture based on the automaximizing bump circuit; we show the effectiveness of this architecture, via software simulation, on a general clustering task. We corroborate our analysis with experimental data from circuits fabricated in a 0.35-µm CMOS process.

Four-quadrant synapse stuff In our first treatments of single-transistor synapses ([1], [2]; elaborated in [3]), we presented the electron-tunneling, hot-electron--injection, and multiplicative behavior of these devices. We used a feedback configuration to characterize the tunneling and hot-electron injection phenomena in these synapses [3]. We also derived an effective learning rule, but we did not consider any specific ways that these synapses could be used in a network. Our presentation of the autozeroing floating-gate amplifier (AFGA) [5], [6] showed the first circuit applications of a single-transistor synapse with continuous oxide currents. In another paper, we generalized the AFGA synapse configuration to consider the behaviors that emerge when single-transistor synapses are coupled together to form various continuoustime learning networks [7]. This paper began to consider these floating-gate devices as continuous-time circuit elements. This paper presents the next fundament a...

Abstract. This paper presents an approach to programming threshold voltages in floating-gate CMOS circuits. The threshold voltage programming is exploited in ultra low-voltage ULV) amplifier design. A threshold voltage programming scheme is presented and several examples of analog ULV circuits are described. The ULV circuits are used in ULV amplifier design. Measured data are provided. 1.

In this paper we present a new, adaptive spatial-derivative circuit for CMOS image sensors. The circuit removes its offset as a natural part of its operation using a combination of electron tunneling and hot-electron injection to add or remove charge on a floating-gate of an auto-zeroing amplifier. We designed, fabricated and successfully tested a chip with the circuit. Test results show that the circuit reduces the offsets by more than an order of magnitude.