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MinMax Timing Analysis and An Application to Asynchronous Circuits
, 1999
"... Modern highperformance asynchronous circuits depend on timing constraints for correct operation, so timing analyzers are essential asynchronous design tools. In this paper, we present a 13valued abstract waveform algebra and a polynomialtime minmax timing simulation algorithm for use in efficien ..."
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Cited by 16 (1 self)
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Modern highperformance asynchronous circuits depend on timing constraints for correct operation, so timing analyzers are essential asynchronous design tools. In this paper, we present a 13valued abstract waveform algebra and a polynomialtime minmax timing simulation algorithm for use in efficient, approximate timing analysis of asynchronous circuits with bounded component delays. Unlike several previous approaches, our algorithm computes separate propagation delay bounds from each circuit input to each internal gate. This is useful for analyzing asynchronous circuits, where the relative transition times of the inputs may not be known a priori, unlike synchronous circuits. We also describe an efficient reconvergent fanout analysis technique that helps in increasing the accuracy of simulation. We have applied our algorithm to build an efficient timing analysis tool for extended burstmode circuits (a class of timingdependent asynchronous circuits) implemented in the 3D design style ...
PolynomialTime Techniques For Approximate Timing Analysis Of Asynchronous Systems
, 1998
"... As designers strive to build systems on chips with ever diminishing device sizes, and as clock speeds of gigahertz and above are being contemplated, the limitations of synchronous circuits are beginning to surface. Consequently, there has been a renewed interest in asyn chronous design techniques t ..."
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Cited by 9 (2 self)
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As designers strive to build systems on chips with ever diminishing device sizes, and as clock speeds of gigahertz and above are being contemplated, the limitations of synchronous circuits are beginning to surface. Consequently, there has been a renewed interest in asyn chronous design techniques that use judicious timing assumptions to obtain fast circuits with low hardware overhead. However, the correct operation of these circuits depend on certain timing constraints being satisfied in the actual implementation. Since statistical variations in manufacturing conditions and operating conditions result in uncertainties in component delays in a chip, it is important to analyze asynchronous systems with uncer tain component delays to check for timing constraint violations and to determine sufficient conditions for their correct operation. Unfortunately, several timing analysis problems are computationally intractable when component delays are uncertain but bounded. This the sis presents polynomialtime techniques for approximate timing analysis of asynchronous systems with bounded component delays. Although the algorithms are conservative in the worst case, experiments indicate that they are fairly accurate in practice.
More Accurate PolynomialTime MinMax Timing Simulation
 in Proceedings of the Third International Symposium on Advanced Research in Asynchronous Circuits and Systems
, 1997
"... We describe a polynomialtime algorithm for minmax timing simulation of combinational circuits. Our algorithm reports conservative bounds on the propagationdelays from each primary input to each gate, for use in the timing verification of fundamentalmode asynchronous circuits. A new reconvergent f ..."
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Cited by 7 (2 self)
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We describe a polynomialtime algorithm for minmax timing simulation of combinational circuits. Our algorithm reports conservative bounds on the propagationdelays from each primary input to each gate, for use in the timing verification of fundamentalmode asynchronous circuits. A new reconvergent fanout analysis technique is presented. Our algorithm produces more accurate results than previous polynomialtime (and some exponentialtime) algorithms in the presence of reconvergent fanouts. 1. Introduction Timing simulation is an important tool for highperformance asynchronous circuit design. However, statistical variations in IC processing conditions, operating conditions, etc., result in uncertainties in component delays which need to be taken into consideration when verifying timingdependent circuit behavior, e.g., hazarddetection in asynchronous circuits. Timing simulation that considers component delays to vary within specified intervals and determines upper and lower bounds on ...
A Timed AutomatonBased Method for Accurate Computation of Circuit Delay in the Presence of CrossTalk
 in the Presence of CrossTalk,” FMCAD’98
, 1998
"... . We present a timed automatonbased method for accurate computation of the delays of combinational circuits. In our method, circuits are represented as networks of timed automata, one per circuit element. The state space of the network represents the evolution of the circuit over time and delay is ..."
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Cited by 6 (1 self)
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. We present a timed automatonbased method for accurate computation of the delays of combinational circuits. In our method, circuits are represented as networks of timed automata, one per circuit element. The state space of the network represents the evolution of the circuit over time and delay is computed by performing a symbolic traversal of this state space. Based on the topological structure of the circuit, a partitioning of the network and a corresponding conjunctively decomposed OBDD representation of the state space is derived. The delay computation algorithm operates on this decomposed representation and, on a class of circuits, obtains performance orders of magnitude better than a nonspecialized traversal algorithm. We demonstrate the use of timed automata for accurate modeling of gate delay and crosstalk. We introduce a gate delay model which accurately represents transistor level delays. We also construct a timed automaton that models delay variations due to crosstalk fo...
Computing Delay with Coupling Using Timed Automata
, 1997
"... ion corresponds to overapproximating F . (ii) Image computation is performed by "propagating wavefronts" across the partitions. This corresponds to performing the composition of the partitions in topological order, and smoothing variables whenever all the G i 's that depend on those variables have b ..."
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Cited by 5 (1 self)
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ion corresponds to overapproximating F . (ii) Image computation is performed by "propagating wavefronts" across the partitions. This corresponds to performing the composition of the partitions in topological order, and smoothing variables whenever all the G i 's that depend on those variables have been composed. As depicted in figure 6, if the set of waveforms at a given cutset has been characterized, all variables to the left of the cutset can be smoothed. This allows minimization and possibly abstraction of the intermediate results. The partitions must be chosen in a way to expedite the image computation. We believe that the following heuristics will work well: ffl As much as possible, create partitions with disjoint support. For such partitions, only the set of possible waveforms at the output nodes need to be stored, the input variables can be hidden. This is not possible for arbitrary partitions, since the correspondence between the output waveforms and the input waveforms need...
Timing Analysis of Combinational Circuits in Intuitionistic Propositional Logic
 Formal Methods in System Design
, 1999
"... Classical logic has so far been the logic of choice in formal hardware verification. This paper proposes the application of intuitionistic logic to the timing analysis of digital circuits. The intuitionistic setting serves two purposes. The modeltheoretic properties are exploited to handle the s ..."
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Cited by 5 (1 self)
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Classical logic has so far been the logic of choice in formal hardware verification. This paper proposes the application of intuitionistic logic to the timing analysis of digital circuits. The intuitionistic setting serves two purposes. The modeltheoretic properties are exploited to handle the secondorder nature of bounded delays in a purely propositional setting without need to introduce explicit time and temporal operators. The proof theoretic properties are exploited to extract quantitative timing information and to reintroduce explicit time in a convenient and systematic way. We present a natural Kripkestyle semantics for intuitionistic propositional logic, as a special case of a Kripke constraint model for Propositional Lax Logic [15], in which validity is validity up to stabilisation, and implication oe comes out as "boundedly gives rise to." We show that this semantics is equivalently characterised by a notion of realisability with stabilisation bounds as realisers...
Characterising Combinational Timing Analyses in Intuitionistic Modal Logic
, 2000
"... The paper presents a new logical specification language, called Propositional Stabilisation Theory (PST), to capture the stabilisation behaviour of combinational inputoutput systems. PST is an intuitionistic propositional modal logic interpreted over sets of waveforms. The language is more economic ..."
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Cited by 3 (2 self)
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The paper presents a new logical specification language, called Propositional Stabilisation Theory (PST), to capture the stabilisation behaviour of combinational inputoutput systems. PST is an intuitionistic propositional modal logic interpreted over sets of waveforms. The language is more economic than conventional specification formalisms such as timed Boolean functions, temporal logic, or predicate logic in that it separates function from time and only introduces as much syntax as is necessary to deal with stabilisation behaviour. It is a purely propositional system but has secondorder expressiveness. One and the same Boolean function can be represented in various ways as a PST formula, giving rise to different timing models which associate different stabilisation delays with different parts of the functionality and adjust the granularity of the datadependency of delays within wide margins. We show how several standard timing analyses can be characterised as algorithms computing c...
Algorithms for Estimating Number of Glitches and Dynamic Power in CMOS Circuits with Delay Variations
 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI
, 2009
"... Dynamic power dissipation of a CMOS VLSI circuit depends on the signal activity at gate outputs. The activity includes the steadystate logic transitions as well as glitches. The latter are a function of gate delays, which, for modern VLSI circuits, have wide processrelated variations. Both average ..."
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Cited by 1 (0 self)
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Dynamic power dissipation of a CMOS VLSI circuit depends on the signal activity at gate outputs. The activity includes the steadystate logic transitions as well as glitches. The latter are a function of gate delays, which, for modern VLSI circuits, have wide processrelated variations. Both average and peak power dissipations are useful and are traditionally estimated by Monte Carlo simulation. This is expensive and the accuracy, especially for peak power, depends upon the number of circuit delay samples that are simulated. We present an alternative. We use zerodelay simulation of a vector pair to determine the steadystate logic activity. We derive lineartime algorithms that, using delay bounds for gates, determine the maximum, minimum and average number of transitions that each gate output can produce. From this information, we estimate the average and peak energy consumed by each vector pair in a given vector set. For a set of random vectors applied to c7552 circuit, our analysis determined the pervector energy consumption as 82.2 picojoules average and 196.3 picojoules peak. In comparison, Monte Carlo simulation of 1,000 circuit samples gave 82.8 picojoules average and 146.1 picojoules peak. The discrepancy of the peak consumption will reduce if more samples were simulated in the Monte Carlo method. Even with 1,000 samples the CPU time of the Monte Carlo analysis was three orders of magnitude greater than the alternative method we offer in this paper.
False Path Analysis in Sequential Circuits
"... : We propose a formulation of the sensitization constraints that must be satisfied by all true paths in a sequential circuit and suggest a number of approximations to these constraints aimed at simplifying their computation while capturing their essential dependencies. Using one of these approximati ..."
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: We propose a formulation of the sensitization constraints that must be satisfied by all true paths in a sequential circuit and suggest a number of approximations to these constraints aimed at simplifying their computation while capturing their essential dependencies. Using one of these approximations we show how an existing combinational timing analysis tool, can be easily augmented to identify false paths in sequential circuits. 1 Introduction The problem of identifying false paths in combinational circuits has been well studied, yet much less effort has been devoted to the identification of false paths in sequential circuits. Such false paths arise as a consequence of the sequential dependencies among the state variables and are overlooked by purely combinational analysis methods. In this paper, we begin by formulating the sequential sensitization constraints that must be satisfied by all true paths in a circuit. We then propose a number of approximations to these constraints aime...
Bounding Switching Activity in CMOS Circuits Using Constraint Resolution
, 1996
"... This paper deals with the problem of estimating the average power consumption (per clock cycle) of CMOS digital circuits. A new patternindependent method is proposed for computing an upper bound on the switching activity, and therefore the average power, of a combinational circuit described at the ..."
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This paper deals with the problem of estimating the average power consumption (per clock cycle) of CMOS digital circuits. A new patternindependent method is proposed for computing an upper bound on the switching activity, and therefore the average power, of a combinational circuit described at the gate level. The method is based on the propagation of abstract waveform sets, described down to the level of individual transitions. The view of a gate as a relation between input and output signals, described by forward and partial inverse functions, permits the determination of a tight upper bound on the power using a constraint resolution method based on waveform narrowing. A fully scalable, case analysisbased algorithm provides at any step an upper bound and, with enough resources (CPU time), it can continue up to the exact solution. The paper presents the theoretical background, a description of the implementation, and results on benchmark circuits. 1. Introduction Both the scaling o...