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Modular Verification of SRT Division
, 1996
"... . We describe a formal specification and mechanized verification in PVS of the general theory of SRT division along with a specific hardware realization of the algorithm. The specification demonstrates how attributes of the PVS language (in particular, predicate subtypes) allow the general theory to ..."
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Cited by 16 (1 self)
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. We describe a formal specification and mechanized verification in PVS of the general theory of SRT division along with a specific hardware realization of the algorithm. The specification demonstrates how attributes of the PVS language (in particular, predicate subtypes) allow the general theory to be developed in a readable manner that is similar to textbook presentations, while the PVS table construct allows direct specification of the implementation's quotient lookup table. Verification of the derivations in the SRT theory and for the data path and lookup table of the implementation are highly automated and performed for arbitrary, but finite precision; in addition, the theory is verified for general radix, while the implementation is specialized to radix 4. The effectiveness of the automation stems from the tight integration in PVS of rewriting with decision procedures for equality, linear arithmetic over integers and rationals, and propositional logic. This example demonstrates t...
Verification of IEEE Compliant Subtractive Division Algorithms
 FORMAL METHODS IN COMPUTERAIDED DESIGN (FMCAD '96)
, 1996
"... A parameterized definition of subtractive floating point division algorithms is presented and verified using PVS. The general algorithm is proven to satisfy a formal definition of an IEEE standard for floating point arithmetic. The utility of the general specification is illustrated using a numb ..."
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Cited by 11 (1 self)
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A parameterized definition of subtractive floating point division algorithms is presented and verified using PVS. The general algorithm is proven to satisfy a formal definition of an IEEE standard for floating point arithmetic. The utility of the general specification is illustrated using a number of different instances of the general algorithm.
Modular Verification of SRT Division
, 1996
"... . We describe a formal specification and verification in PVS for the general theory of SRT division, and for the hardware design of a specific implementation. The specification demonstrates how attributes of the PVS language (in particular, predicate subtypes) allow the general theory to be deve ..."
Abstract

Cited by 11 (1 self)
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. We describe a formal specification and verification in PVS for the general theory of SRT division, and for the hardware design of a specific implementation. The specification demonstrates how attributes of the PVS language (in particular, predicate subtypes) allow the general theory to be developed in a readable manner that is similar to textbook presentations, while the PVS table construct allows direct specification of the implementation's quotient lookup table. Verification of the derivations in the SRT theory and for the data path and lookup table of the implementation are highly automated and performed for arbitrary, but finite precision; in addition, the theory is verified for general radix, while the implementation is specialized to radix 4. The effectiveness of the automation derives from PVS's tight integration of rewriting with decision procedures for equality, linear arithmetic over integers and rationals, and propositional logic. This example demonstrates t...
Verification of FloatingPoint Adders
 LECTURE NOTES IN COMPUTER SCIENCE
, 1998
"... The floatingpoint(FP) division bug in Intel's Pentium processor and the overflow flag erratum of the FIST instruction in Intel's Pentium Pro and Pentium II processor have demonstrated the importance and the difficulty of verifying FP arithmetic circuits. In this paper, we present the verificatio ..."
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Cited by 8 (0 self)
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The floatingpoint(FP) division bug in Intel's Pentium processor and the overflow flag erratum of the FIST instruction in Intel's Pentium Pro and Pentium II processor have demonstrated the importance and the difficulty of verifying FP arithmetic circuits. In this paper, we present the verification of FP adders with reusable specifications, using extended wordlevel SMV, which is improved by using the Multiplicative Power HDDs (*PHDDs), and by incorporating conditional symbolic simulation as well as a shortcircuiting technique. Based on the case analysis, the specifications of FP adders are divided into several hundreds of implementationindependent subspecifications. We applied our system and these specifications to verify the IEEE double precision FP adder in the Aurora III Chip at the University of Michigan. Our system found several design errors in this FP adder and generated one counterexample for each error within several minutes. A variant of the corrected FP adder is created to illustrate the capability of our system to handle different FP adder designs. For each of FP adders, the verification task finished in 2 CPU hours on a Sun UltraSPARCII server.
Hierarchical verification of the implementation of the ieee754 tabledriven floatingpoint exponential function using hol
 In International Conference on Theorem Proving in HigherOrder Logics (TPHOLs’01
, 2001
"... Abstract. The IEEE754 floatingpoint standard is considered one of the most important standards, and is used in nearly all floatingpoint applications. In this paper, we have formalized and verified a hardware implementation of the TableDriven algorithm for the floatingpoint exponential function. ..."
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Cited by 1 (0 self)
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Abstract. The IEEE754 floatingpoint standard is considered one of the most important standards, and is used in nearly all floatingpoint applications. In this paper, we have formalized and verified a hardware implementation of the TableDriven algorithm for the floatingpoint exponential function. Throughout this paper, we have used a hierarchical approach in formally modeling and verifying in HOL the floatingpoint exponential function from the gate level implementation up to a behavioral specification written by Harrison [7]. 1
A Hierarchical Verification of The IEEE754 TableDriven Floating Point Exponential Function using HOL
, 2001
"... ..."
Hierarchical Verification of TwoDimensional HighSpeed Multiplication in PVS: A Case Study
, 1996
"... It is shown how to use the PVS specification language and proof checker to present a hierarchical formalization of a twodimensional, highspeed integer multiplier on the gate level. We first give an informal description of iterative array multiplier circuits together with a natural refinement into v ..."
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It is shown how to use the PVS specification language and proof checker to present a hierarchical formalization of a twodimensional, highspeed integer multiplier on the gate level. We first give an informal description of iterative array multiplier circuits together with a natural refinement into vertical and horizontal stages, and then show how the various features of PVS can be used to obtain a readable, highlevel specification. The verification exploits the tight integration between rewriting, arithmetic decision procedures, and equality that is present in PVS. Altogether, this case study demonstrates that the resources of an expressive specification language and of a generalpurpose theorem prover permit highly automated verification in this domain, and can contribute to clarity, generality, and reuse. 1 Introduction Verifying functional correctness results about arithmetic circuits poses some serious challenges to current hardware verification techniques. Almost all automated a...
Design Structures for Formally Verified Floating Point Units
, 1997
"... A design structure is presented to assist in the design of IEEE compliant floating point hardware. The basis of the process is an abstraction of the bitwise operations found in hardware to reals and integers. This simplifies the definition of functionality prior to going to hardware. The final desig ..."
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A design structure is presented to assist in the design of IEEE compliant floating point hardware. The basis of the process is an abstraction of the bitwise operations found in hardware to reals and integers. This simplifies the definition of functionality prior to going to hardware. The final design structure will include a set of general algorithms defined for floating point operations (add, sub, multiply, division, square root) which are verified with respect to the IEEE standard. The designer then instantiates the general algorithms to complete the algorithmic specification. The algorithms are then mapped to hardware, maintaining the abstraction. The result is a verified functional description of the hardware which can then be realized by conventional techniques or by refining the description to bitwise operations. This paper is a work in progress which describes the design process to get a functional description of the hardware. Current work has focused on subtractive division and...