Abstract—Precision amplifiers dominate the power dissipation in most high-speed pipelined analog-to-digital converters (ADCs). We propose a digital background calibration technique as an enabling element to replace precision amplifiers by simple powerefficient open-loop stages. In the multibit first stage of a 12-bit 75-MSamples/s proof-of-concept prototype, we achieve more than 60 % residue amplifier power savings over a conventional implementation. The ADC has been fabricated in a 0.35- m double-poly quadruple-metal CMOS technology and achieves typical differential and integral nonlinearity within 0.5 LSB and 0.9 LSB, respectively. At Nyquist input frequencies, the measured signal-to-noise ratio is 67 dB and the total harmonic distortion is 74 dB. The IC consumes 290 mW at 3 V and occupies 7.9 mmP. Index Terms—Analog-to-digital conversion, adaptive systems, calibration, CMOS analog integrated circuits, linearization techniques, parameter estimation. I.

Abstract—A low-power CMOS reconfigurable analog-to-digital converter that can digitize signals over a wide range of bandwidth and resolution with adaptive power consumption is described. The converter achieves the wide operating range by (1) reconfiguring its architecture between pipeline and delta–sigma modes; (2) varying its circuit parameters, such as size of capacitors, length of pipeline, and oversampling ratio, among others; and (3) varying the bias currents of the opamps in proportion to the converter sampling frequency, accomplished through the use of a phase-locked loop (PLL). This converter also incorporates several power-reducing features such as thermal noise limited design, global converter chopping in the pipeline mode, opamp scaling, opamp sharing between consecutive stages in the pipeline mode, an opamp chopping technique in the delta–sigma mode, and other design techniques. The opamp chopping technique achieves faster closed-loop settling time and lower thermal noise than conventional design. At a converter power supply of 3.3 V, the converter achieves a bandwidth range of 0–10 MHz over a resolution range of 6–16 bits, and parameter reconfiguration time of twelve clock cycles. Its PLL lock range is measured at 20 kHz to 40 MHz. In the delta–sigma mode, it achieves a maximum signal-to-noise ratio of 94 dB and second and third harmonic distortions of 102 and 95 dB, respectively, at 10 MHz clock frequency, 9.4 kHz bandwidth, and 17.6 mW power. In the pipeline mode, it achieves a maximum DNL and INL of 0.55 LSBs and 0.82 LSBs, respectively, at 11 bits, at a clock frequency of 2.6 MHz and 1 MHz tone with

analog-to-digital converter (ADC) using a passive capacitor erroraveraging technique and a nested CMOS gain-boosting technique is described. The converter is optimized for low-voltage low-power applications by applying an optimum stage-scaling algorithm at the architectural level and an opamp and comparator sharing technique at the circuit level. Prototyped in a 0.18- m 6M-1P CMOS process, this converter achieves a peak signal-to-noise plus distortion ratio (SNDR) of 75.5 dB and a 103-dB spurious-free dynamic range (SFDR) without trimming, calibration, or dithering. With a 1-MHz analog input, the maximum differential nonlinearity is 0.47 LSB and the maximum integral nonlinearity is 0.54 LSB. The large analog bandwidth of the front-end sample-and-hold circuit is achieved using bootstrapped thin-oxide transistors as switches, resulting in an SFDR of 97 dB when a 40-MHz full-scale input is digitized. The ADC occupies an active area of 10 mmP and dissipates 98 mW. Index Terms—Analog integrated circuits, capacitor mismatch, comparator sharing, discrete-time common-mode voltage regulation, early comparison, low power, low voltage, nested CMOS gain boosting, opamp sharing, passive capacitor error-averaging, pipeline analog-to-digital converter, pseudo-differential, subsampling. I.

A 12-bit 20-Msample/s pipelined analog-to-digital converter (ADC) is calibrated in the background using an algorithmic ADC, which is itself calibrated in the foreground. The overall calibration architecture is nested. The calibration overcomes the circuit nonidealities caused by capacitor mismatch and finite operational amplifier (opamp) gain both in the pipelined ADC and the algorithmic ADC. With a 58-kHz sinusoidal input, test results show that the pipelined ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 70.8 dB, a peak spurious-free-dynamic range (SFDR) of 93.3 dB, a total-harmonic distortion (THD) of –92.9 dB, and a peak integral nonlinearity (INL) of 0.47 least-significant bit (LSB). The total power dissipation is 254 mW from 3.3 V. The active area is 7.5 mm 2 in 0.35-µm CMOS.

A 12-b 20-MS/s pipelined ADC is calibrated using an algorithmic ADC, which is itself calibrated. With background calibration, the peak SNDR and SFDR of the pipeline are 70.8 dB and 93.3 dB, respectively. The total power dissipation is 254 mW from 3.3 V. The active area is 7.5 mm 0.35 ¡ in m CMOS. I.

The implementation of active pixel based image sensors in CMOS technology is becoming increasingly important forproducing imaging systems that can be manufactured with low cost, low power, simple interface, and with good image quality. The major obstacle in the design of CMOS imagers is Fixed Pattern Noise (FPN) and Signal-to-Noise-Ratio (SNR) of the video output. This research focuses on minimizing FPN and improving SNR in linear CMOS image sensors which are needed in scanning and swiping applications such as nger print sensing, spectroscopy, and medical imaging systems. FPN is reduced in this research through the use of closed loop operational ampli ers in active pixels and through performing Correlated Double Sampling (CDS). SNR is improved by increasing the pixel saturation voltage. This thesis concludes that FPN can be reduced using the closed loop opamp bu ers. The major FPN noise sources are the shot noise from the photodiode, kTC noise from the sampling capacitors, and o set mismatches in the sample and hold ampli ers all of which are not compensated by CDS. Sample and hold ampli er o set mismatch is identi ed as

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The power dissipation of an analog-to-digital converter (ADC) is a function of many variables, such as sampling rate (f S), resolution, architecture, process, voltage supply and technology. This chapter will attempt to establish the power dependence on sampling rate and resolution as its primary goal. To make this tenable, the scope of this task will be nar-rowed in the following two ways: 1. Architectures: Only those ADC’s suitable for use in high-speed signal processing applications, i.e., capable of attaining high Nyquist sampling rates, such as Flash, Two-step, Subranging, Folding, Interpolating and Pipelined architectures will be considered. 2. Process: Coverage will be restricted to high-integration capable IC processes such as bipolar, BiCMOS and CMOS processes which allow embedding of the ADC function in a monolithic signal processing chip. Even with a narrower scope, only a first-order analysis is attempted in light of the many variables that influence the power of an ADC. After developing power relationships for the above A/D architectures, the results of this analysis will be used to estimate the power 1 High-Speed ADC Architectures 2 variation in three high-speed system examples. 2.1 High-Speed ADC Architectures Before describing each architecture type, data gathered from published research of these types of ADC’s is presented for reference. In Fig.2-1, the resolution of the ADC’s is

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