Abstract—The problem of low-voltage operation of switched-capacitor circuits is discussed, and several solutions based on using unity-gain-reset of the opamps are proposed. Due to the feedback structure, the opamps do not need to be switched off during the reset phase of the operation, and hence can be clocked at a high rate. A low-voltage 16 modulator, incorporating pseudodifferential unity-gain-reset opamps, is described. A test chip, realized in a 0.35- m CMOS process and clocked at 10.24 MHz, provided a dynamic range of 80 dB and a signal-to-noise C distortion (SNDR) ratio of 78 dB for a 20-kHz signal bandwidth, and a dynamic range of 74 dB and SNDR of 70 dB for a 50-kHz bandwidth, with a 1-V supply voltage. Index Terms—ADC, charge-pump circuits, delta–sigma, low voltage, sigma–delta, switched-capacitor circuits, switched opamp. I.

Abstract—This work presents a study of the extended counting technique for a 1.2-V micropower voice-band A/D converter. This extended counting technique is a blend of 61 modulation with its high resolution but relatively low speed and algorithmic conversion with its higher speed but lower accuracy. To achieve this, the converter successively operates first as a first-order 61 modulator to convert the most significant bits, and then the same hardware is used as an algorithmic converter to convert the remaining least significant bits. An experimental prototype was designed in 0.8- m CMOS. With a 1.2-V power supply, it consumes 150 W of power at a 16-kHz Nyquist sampling frequency. The measured peak ƒ @x C „rhA was 80 dB and the dynamic range 82 dB. The converter core including the controller and all reconstruction logic occupies about I Q I mmP of chip area. This is considerably less than a complete 61 modulation A/D converter where the digital decimation filter would occupy a significant amount of chip area. Index Terms—Analog-to-digital, extended counting, low power, low voltage. I.

A charge pump circuit realized with the substrateisolated polysilicon diode in the 0.25-m CMOS process is proposed. With the polysilicon diode, the stable negative voltage generation can be realized in general sub-quartermicron CMOS process without extra process modification or additional mask layer. The device characteristic of polysilicon diode and the voltage waveforms of the negative charge pump circuit have been successfully verified in a 0.25-m CMOS process with grounded p-type substrate.

Abstract- In this paper we discuss the design of a low-voltage (1.5V), continuous-time, biquadratic CMOS filter based on Dynamic Gate Biasing (DGB). We begin by discussing the filter’s structure and its tuning mechanism. The filter uses transconductance-C cells and implements low-pass, bandpass and highpass transfer functions. The transconductances are tuned using the gate voltages of MOSFETs operating in the triode region. We review the principle of DGB, and discuss the design of the charge pump based on the filter’s performance and tunability requirements. Circuit details of the filter elements and the charge pump are presented along with SPICE simulation results of the overall filter. I.

Abstract- In this paper we review the genesis of charge pump circuits, their evolution and improvement in design and their importance in nonvolatile memory circuits, low-voltage analog building blocks and other applications. I.

The paper describes switched-capacitor dc-dc converters (charge pumps) suitable for on-chip, low-power applications. The proposed configurations are based on connecting two identical but opposite-phase SC converters in parallel, thus eliminating the need for separate bootstrap gate drivers. We focus on emerging very low-power VLSI applications such as batterypowered or self-powered signal processors where high power conversion efficiency is important and where power levels are in the milliwatt range. Conduction and switching losses are considered to allow design optimization in terms of switching frequency and component sizes. Open-loop and closed-loop operation of an experimental, fully integrated, 10MHz voltage doubler is described. The doubler has 2V or 3V input and generates 3.3V or 5V output at up to 5mW load. The converter circuit fabricated in a standard 1.2 CMOS technology takes 0.7mm 2 of the chip area. 1 Introduction Switched-capacitor (SC) dc-dc converters (also called "...

Abstract—A new charge-pump circuit with the controllable body voltage is proposed. By adjusting the body voltage, the back bias effect is removed and the threshold voltage of the MOSFET used as a switch is kept constant. With no threshold voltage increase, higher output voltage than the conventional charge pump can be obtained in the proposed charge pump. With two auxiliary MOSFET’s used to update the body voltage, the proposed charge pump shows compatible performance of the ideal diode charge pump. Index Terms—Auxiliary MOSFET, body effect, charge pump, threshold voltage.

Abstract-- An algebraic model that describes the operation of binary Switched-Capacitor Converters (SCC) was developed and generalized to any radix case. The proposed approach reduces the power loss by increasing the number of target voltages. In the binary case, the flying capacitors are automatically kept charged to binary weighted voltages and consequently, the resolution of the possible target voltages is binary. The paper presents the underlining theory of the proposed SCC and two new control methods to regulate the output voltage. It is shown that the theoretical formulation of the new number systems can describe many SCC circuits on the market and can help design new SCC with a larger number of target voltages. The theoretical results were verified for the binary case by simulation and experimentally. Excellent agreement was found between the theory and experimental