Abstract—In this paper, we consider cost-effective designs of wavelength division multiplexing (WDM) optical switching networks for current and future generation communication systems. Based on different target applications: we categorize WDM optical switching networks into two connection models: the wavelength-based model and the fiberlink-based model. Most of existing WDM optical switching networksbelongtothefirst category. In this paper we present new designs for WDM optical switching networks under both models by using sparse crossbar switches instead of full crossbar switches in combination with wavelength converters. The newly designed sparse WDM optical switching networks have minimum hardware cost in terms of both the number of crosspoints and the number of wavelength converters. The single stage and multistage implementations of the sparse WDM optical switching networks are considered. An optimal routing algorithm for the proposed sparse WDM optical switching networks is also presented. Index Terms—Wavelength division multiplexing (WDM), optical switching networks, optical switches, network architectures, sparse crossbars, concentrators, wavelength conversion, permutation, multicast, multistage networks. I.

Abstract- The inclusion of programmable logic cores in modern SoCs motivates the need for an access network to make full use of this resource. The programmable nature of these cores removes the requirement of input/output ordering on this access network. Theoretical work on a class of unordered networks called concentrators has shown that as these networks become large, they have a lower cost than ordered or permutation networks. However, currently known constructions of concentrator networks are not lower cost than permutation networks for the entire range of networks of the size required for SoCs. This paper demonstrates the differences in the cost and depth of concentrator and permutation networks. It will also present a new construction of a concentrator network that has lower cost and depth than a permutation network for all configurations. I.

In this paper, we study the performance of packet concentrators with input queueing. A recent concentrator model given by Gunduzhan and Oruc considers packet concentrators with di#erent input and output packet rates and gives a minimum crosspoint complexity construction for bu#ered sparse crossbar concentrators. We use this model as a basis for the performance evaluation of concentrators which queue packets at the inputs and have di#erent input and output packet rates. It is shown that for input queueing, with constant size packets and independent batch arrivals, the best performance can be represented by a GI /D/c queueing system. Using this result we provide explicit solutions for the probability distribution of queue occupancy and packet delay for binomial packet arrivals. Good tail approximations for quick calculations of bu#er size and packet delay for a given probability of packet loss are also given.

In this paper, we consider packet switching problems in bipartite concentrators under the assumption that more than one packet/slot can be processed through a fabric crosspoint. We use three packet-processing models to derive the packet loss and throughput in a bipartite concentrator. The following paper is an extended summary which presents the models and main results. We expect to provide a more rigorous account of our results and analysis in a full paper in the future.

The theory of multirate switching networks, started in the late 80s, has been very practically useful. In particular, it has served as the theoretical foundation for the development of most Asynchronous Transfer Mode (ATM) switching systems. Rearrangeable multirate multicast switching networks are customarily called rearrangeable multirate distributors. It has been known for more than 18 years that rearrangeable multirate distributors with cross-point complexity O(n log 2 n) can be constructed, where n is the number of inputs (and outputs) of the switching network. The problem of constructing optimal distributors remains open thus far. In this paper, we give a general construction of rearrangeable multirate distributors with given depths. One of the rewards of our construction is a rearrangeable multicast distributor with cross-point complexity O(n log n). We shall also show that this cross-point complexity is optimal, thus settling the aforementioned open problem. One of the key ingredients of our new construction is the notion of multirate concentrators. The second ingredient is a multirate version of the Pippenger network, which is a rearrangeable multirate distributor recursively constructed based on multirate concentrators. We shall show how to construct given-depth multirate concentrators and given-depth multirate Pippenger networks with small sizes. When the depth is chosen to optimize the size, we obtain the aforementioned O(n log n) cross-point complexity.

Abstract—This paper proposes a systematic strategy to efficiently explore the design space of field-programmable gate array (FPGA) routing architectures. The key idea is to use stochastic methods to quickly locate near-optimal solutions in designing FPGA routing architectures without exhaustively enumerating all design points. The main objective of this paper is not as much about the specific numerical results obtained, as it is to show the applicability and effectiveness of the proposed optimization approach. To demonstrate the utility of the proposed stochastic approach, we developed the tool for optimizing routing architecture (TORCH) software based on the versatile place and route tool [1]. Given FPGA architecture parameters and a set of benchmark designs, TORCH simultaneously optimizes the routing channel segmentation and switch box patterns using the performance metric of average interconnect power-delay product estimated from placed and routed benchmark designs. Special techniques—such as incremental routing, infrequent placement, multi-modal move selection, and parallelized metric evaluation— are developed to reduce the overall run time and improve the quality of results. Our experimental results have shown that the stochastic design strategy is quite effective in co-optimizing both routing channel segmentation and switch patterns. With the optimized routing architecture, relative to the performance of our chosen architecture baseline, TORCH can achieve average improvements of 24 % and 15 % in delay and power consumption for the 20 largest Microelectronics Center of North Carolina benchmark designs, and 27 % and 21 % for the eight benchmark designs synthesized with the Altera Quartus II University Interface Program tool. Additionally, we found that the average segment length in an FPGA routing channel should decrease with technology scaling. Finally, we demonstrate the versatility of TORCH by illustrating how TORCH can be used to optimize other aspects of the routing architecture in an FPGA. Index Terms—Design exploration, FPGA, routing architecture, stochastic.