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Reasoning Theories  Towards an Architecture for Open Mechanized Reasoning Systems
, 1994
"... : Our ultimate goal is to provide a framework and a methodology which will allow users, and not only system developers, to construct complex reasoning systems by composing existing modules, or to add new modules to existing systems, in a "plug and play" manner. These modules and systems ..."
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Cited by 47 (11 self)
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: Our ultimate goal is to provide a framework and a methodology which will allow users, and not only system developers, to construct complex reasoning systems by composing existing modules, or to add new modules to existing systems, in a "plug and play" manner. These modules and systems might be based on different logics; have different domain models; use different vocabularies and data structures; use different reasoning strategies; and have different interaction capabilities. This paper makes two main contributions towards our goal. First, it proposes a general architecture for a class of reasoning systems called Open Mechanized Reasoning Systems (OMRSs). An OMRS has three components: a reasoning theory component which is the counterpart of the logical notion of formal system, a control component which consists of a set of inference strategies, and an interaction component which provides an OMRS with the capability of interacting with other systems, including OMRSs and hum...
Extending the HOL theorem prover with a Computer Algebra System to Reason about the Reals
 Higher Order Logic Theorem Proving and its Applications (HUG `93
, 1993
"... In this paper we describe an environment for reasoning about the reals which combines the rigour of a theorem prover with the power of a computer algebra system. 1 Introduction Computer theorem provers are a topic of research interest in their own right. However much of their popularity stems from ..."
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Cited by 33 (4 self)
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In this paper we describe an environment for reasoning about the reals which combines the rigour of a theorem prover with the power of a computer algebra system. 1 Introduction Computer theorem provers are a topic of research interest in their own right. However much of their popularity stems from their application in computeraided verification, i.e. proving that designs of electronic or computer systems, programs, protocols and cryptosystems satisfy certain properties. Such proofs, as compared with the proofs one finds in mathematics books, usually involve less sophisticated central ideas, but contain far more technical Supported by the Science and Engineering Research Council, UK. y Supported by SERC grant GR/G 33837 and a grant from DSTO Australia. details and therefore tend to be much more difficult for humans to write or check without making mistakes. Hence it is appealing to let computers help. Some fundamental mathematical theories, such as arithmetic, are usually requi...
DDDFM9001: Derivation of a Verified Microprocessor
, 1994
"... Derivation and verification represent alternate approaches to design. Derivation aims at deriving a "correct by construction" design while verification aims at constructing a post factum "proof of correctness" for a design. However, as researchers and engineers gain design experi ..."
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Cited by 22 (6 self)
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Derivation and verification represent alternate approaches to design. Derivation aims at deriving a "correct by construction" design while verification aims at constructing a post factum "proof of correctness" for a design. However, as researchers and engineers gain design experience in a formal framework, both approaches are emerging as interdependent facets of design. The thesis of this work is that alternate forms of formal reasoning must be integrated if formal methods are to support the natural analytical and generative reasoning that takes place in engineering practice. As a vehicle for this research, the DDD digital design derivation system was implemented to study formal hardware design in an algebraic framework. DDD is a firstorder transformation system which mechanizes a basic design algebra for synthesizing digital circuit descriptions from highlevel functional specifications. The system is a collection of correctness preserving transformations that promote a topdown desig...
Towards a Verification Technique for Large Synchronous Circuits
 Bell Labs
, 1992
"... We presentasymbolic simulation based verification approach which can be applied to large synchronous circuits. A new technique to encode the state and input constraints as parametric Boolean expressions over the state and input variables is used to make our symbolic simulation based verification ..."
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Cited by 2 (0 self)
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We presentasymbolic simulation based verification approach which can be applied to large synchronous circuits. A new technique to encode the state and input constraints as parametric Boolean expressions over the state and input variables is used to make our symbolic simulation based verification approach efficient. The constraints which are encoded through parametric Boolean expressions can involve the Boolean connectives (\Delta#+ # :), the relational operators (!# #?## 6=# =), and logical connectives (#). This technique of using parametric Boolean expressions vastly reduces the number of symbolic simulation vectors and the time for verification. Our verification approach can also be applied for efficient modular verification of large designs# the technique used is to verify each constituent submodule separately,however in the context of the overall design. Since regular arrays are part of many large designs, we havedeveloped an approach for the verification of regular arrays which combines formal verification at the high level and symbolic simulation at the lowlevel(e.g., switchlevel). Weshowtheverification of a circuit called Minmax, a pipelined cache memory system, and an LRU array implementation of the least recently used block replacement policy,toillustrate our verification approach. The experimental results are obtained using the COSMOS symbolic simulator.
SequentialSystem Factorization
, 1995
"... The success of highlevel synthesis methods in reducing design time and formal verification methods in reducing design errors in digital VLSI circuits have opened the way to systemlevel synthesis and verification. Derivation is a form of formal verification that deals with correctbyconstruction r ..."
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The success of highlevel synthesis methods in reducing design time and formal verification methods in reducing design errors in digital VLSI circuits have opened the way to systemlevel synthesis and verification. Derivation is a form of formal verification that deals with correctbyconstruction reasoning. A set of equivalence preserving transformations are used to derive an implementation from a specification. A key step in derivation is to impose an architectural structure on a behavioral specification by factoring functional behavior into abstract components [40]. These system factorization transformations impose a naive model for synchronization and data communication between components in a system. The thesis of this work is that system factorization must be generalized to support arbitrary interaction protocols between components in a system for derivational methodology to be useful in systemlevel design. This dissertation develops a general transformation to decompose a seque...
Verification of VLSI Circuits: Signal Value Modeling and HDL Translation
"... . The ever increasingly number of transistors possible in VLSI circuits compounds the difficulty in ensuring correct designs. Formal verification has been touted as a means of overcoming this problem, but most of the work in this area has been directed at standalone theorem provers. Before verificat ..."
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. The ever increasingly number of transistors possible in VLSI circuits compounds the difficulty in ensuring correct designs. Formal verification has been touted as a means of overcoming this problem, but most of the work in this area has been directed at standalone theorem provers. Before verification is accepted by the VLSI design community, the stand alone verification tools that are in use in the research community must be integrated with the CAD tools used by designers. The primary obstacle is that the hardware description languages (HDL's) used in verification tools are often not syntactically or semantically compatible with the hardware description languages commonly used in the VLSI design community. The research presented in this paper is directed at this problem. We have built a parser for the BOLT hardware description language in the HOL theorem proving system. This provides a means of using the same language in the theorem proving system and the VLSI CAD tools used in our ...