High-performance processors use a large set-associative L1 data cache with multiple ports. As clock speeds and size increase such a cache co nsumes a significant percentageo f the to tal pro cesso energy. This paper pro oses a method o saving energy by reducing the number of data cache accesses. It do esso by mo difying the Lo6 /Stoq Queue design to allo w "caching" o prev io sly accessed data valueso nbo h lo ads and sto res after the co rrespo nding memo ry access instruct io has beenco mitted. It is sho wn that a 32-entry mo dified LSQ designallo ws an averageo 38.5%o the loq s in the SpecINT95 benchmarks and 18.9% in the SpecFP95 benchmarks to get their data fro the LSQ. The reductio in the numbero f L1 cache accesses results in upto a 40% reductio n in the L1 data cache energy co nsumptio n and in an upto a 16% impro vement in the energy--delaypro duct while requiring almox no additioal hardware or complex control logic.