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DETERMINANT MAXIMIZATION WITH LINEAR MATRIX INEQUALITY CONSTRAINTS
"... The problem of maximizing the determinant of a matrix subject to linear matrix inequalities arises in many fields, including computational geometry, statistics, system identification, experiment design, and information and communication theory. It can also be considered as a generalization of the s ..."
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Cited by 229 (18 self)
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The problem of maximizing the determinant of a matrix subject to linear matrix inequalities arises in many fields, including computational geometry, statistics, system identification, experiment design, and information and communication theory. It can also be considered as a generalization of the semidefinite programming problem. We give an overview of the applications of the determinant maximization problem, pointing out simple cases where specialized algorithms or analytical solutions are known. We then describe an interiorpoint method, with a simplified analysis of the worstcase complexity and numerical results that indicate that the method is very efficient, both in theory and in practice. Compared to existing specialized algorithms (where they are available), the interiorpoint method will generally be slower; the advantage is that it handles a much wider variety of problems.
A PrecorrectedFFT Method for Electrostatic Analysis of Complicated 3D Structures
 IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems
, 1997
"... In this paper we present a new algorithm for accelerating the potential calculation which occurs in the inner loop of iterative algorithms for solving electromagnetic boundary integral equations. Such integral equations arise, for example, in the extraction of coupling capacitances in threedimensio ..."
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Cited by 132 (45 self)
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In this paper we present a new algorithm for accelerating the potential calculation which occurs in the inner loop of iterative algorithms for solving electromagnetic boundary integral equations. Such integral equations arise, for example, in the extraction of coupling capacitances in threedimensional (3D) geometries. We present extensive experimental comparisons with the capacitance extraction code FASTCAP [1] and demonstrate that, for a wide variety of geometries commonly encountered in integrated circuit packaging, onchip interconnect and microelectromechanical systems, the new "precorrectedFFT " algorithm is superior to the fast multipole algorithm used in FASTCAP in terms of execution time and memory use. At engineering accuracies, in terms of a speedmemory product, the new algorithm can be superior to the fast multipole based schemes by more than an order of magnitude.
Rapid Solution of Potential Integral Equations in Complicated 3Dimensional Geometries
, 1997
"... Analysis of many electromagnetic problems in engineering, such as electromagnetic interference (EMI) calculations or estimation of interconnnect coupling capacitances and inductances, is often performed via numerical methods based on integral equations. Analysis of the comphcated threedimensional&a ..."
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Cited by 10 (0 self)
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Analysis of many electromagnetic problems in engineering, such as electromagnetic interference (EMI) calculations or estimation of interconnnect coupling capacitances and inductances, is often performed via numerical methods based on integral equations. Analysis of the comphcated threedimensional' geometries of modern engineering structures requires efficient algorithms to solve the large, dense linear systems generated by integral equation techniques. This thesis develops and analyzes a gridbased, "precorrectedFFT" method which preserves the efficiency of recently developed fastmultipole techniques but is more easily generalizable to a variety of kernels, and may have substantial performance benefits for commonly encountered geometries. The proposed
Generalized Darlington synthesis
 IEEE Trans. Circ. Syst. – I: Fund. Theory Appl
, 1999
"... In honor to the great scientist and engineer Sidney Darlington Abstract — The existence of a “Darlington embedding ” has been the topic of vigorous debate since the time of Darlington’s original attempts at synthesizing a lossy input impedance through a lossless cascade of sections terminated in a u ..."
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Cited by 7 (1 self)
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In honor to the great scientist and engineer Sidney Darlington Abstract — The existence of a “Darlington embedding ” has been the topic of vigorous debate since the time of Darlington’s original attempts at synthesizing a lossy input impedance through a lossless cascade of sections terminated in a unit resistor. This paper gives a survey of present insights in that existential question. In the first part it considers the multiport, time invariant case, and it gives the necessary and sufficient conditions for the existence of the Darlington embedding, namely that the matrix transfer scattering function considered must satisfy a special property of analyticity known as “pseudomeromorphic continuability ” (of course aside from the contractivity condition which ensures lossiness). As a result, it is reasonably easy to construct passive impedances or scattering functions which do not possess a Darlington embedding, but they will not be rational, i.e. they will have infinite dimensional state spaces. The situation changes dramatically when timevarying systems are concerned. In this case also Darlington synthesis is possible and attractive, but the anomalous case where no synthesis is possible already occurs for systems with finite dimensional state spaces. We give precise conditions for the existence of the Darlington synthesis for the timevarying case as well. It turns out that the main workhorse in modern Darlington theory is the geometry of the so called Hankel map of the scattering transfer function to be embedded. This fact makes Darlington theory of considerably larger importance for the understanding of systems and their properties than the original synthesis question would seem to infer. Although the paper is entirely devoted to the theoretical question of existence of the Darlington embedding and its system theoretic implications, it does introduce the main algorithm used for practical Darlington synthesis, namely the ‘square root algorithm ’ for external or innerouter factorization, and discusses some of its implications in the final section. I.
Circuit Models For The Hybrid Element Method
 in Proc. Int. Symp. on Circuits and Systems
, 1996
"... In this paper, we describe a new hybrid method which combines the boundary element method (BEM) and the finite element method (FEM) to calculate the circuit models for layout dependent capacitances in VLSI circuits. The hybrid method which we present does more than solving a particular field problem ..."
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In this paper, we describe a new hybrid method which combines the boundary element method (BEM) and the finite element method (FEM) to calculate the circuit models for layout dependent capacitances in VLSI circuits. The hybrid method which we present does more than solving a particular field problem, it produces a good physical circuit model for the interface between the regions where the BEM and the FEM are applied. We show fast convergence of the hybrid method and give 2D and 3D simulation results which confirm its validity. 1. INTRODUCTION The parasitic interconnect capacitances in integrated circuits (IC's) have significant influence on the circuit performance. In order to verify, via simulation, correct behavior of IC's before costly fabrication, these capacitances must be calculated from the layout design of the circuit (capacitance extraction). Until now, the boundary element method was the most popular technique employed for accurate capacitance modeling [3], [4], [5], [6], [8...
A Hybrid Element Method For Calculation Of Capacitances From The Layout Of Integrated Circuits
, 1996
"... We describe a hybrid method which combines the boundary element method (BEM) and the finite element method (FEM) to compute circuit models for layout dependent capacitances. The method can handle irregularities in the stratification of the layout of the integrated circuits (IC's). New in the me ..."
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Cited by 1 (1 self)
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We describe a hybrid method which combines the boundary element method (BEM) and the finite element method (FEM) to compute circuit models for layout dependent capacitances. The method can handle irregularities in the stratification of the layout of the integrated circuits (IC's). New in the method are the models for the interface between the regions where the BEM and the FEM are applied. We show fast convergence of the method and give 2D and 3D simulation results which confirm its validity. 1 Introduction Parasitic interconnect capacitances in integrated circuits have significant influence on circuit performance. To verify correct behavior of IC's before costly fabrication, these capacitances must be calculated (extracted) from the layout design (geometry) of the circuit. The most popular techniques used for capacitance extraction are the BEM (Brebbia[2], Ruehli[5], Dewilde[3]) and the bulk FEM (Silvester[7]). For regular media as depicted in Fig.(1a), the BEM is computationally more...
EFFICIENT PEEC MODELING OF MULTILAYER BOARDS AND MULTICHIP MODULES
"... Abstract: MultiChip Modules (MCM) for high speed digital applications use meshed planes between the signal layers for shielding and power supply. Both wave impedances of the signal lines and coupling behavior between different signal layers are influenced by the properties of these meshed planes. T ..."
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Abstract: MultiChip Modules (MCM) for high speed digital applications use meshed planes between the signal layers for shielding and power supply. Both wave impedances of the signal lines and coupling behavior between different signal layers are influenced by the properties of these meshed planes. Together with the quick increase of operating frequency of highspeed integrated circuits (IC), this may cause problems such as dispersion, crosstalk, and packaging effects which must be investigated by means of simulations. The Partial Elements Equivalent Circuit (PEEC) method has proven to be suitable to deal with such systems, particularly to investigate ground bounce effects. For analysis of large interconnect and packaging structures, however, the computing time increases very rapidly with the system’s complexity. To reduce the costs of calculation, especially for inductance and capacitance calculation, a method is introduced that leads to both accurate and fast results. The validity of the modeling is verified with Sparameter calculations of blocking measures in a multilayer board and shall be used for investigations of multichip modules. 1.
A Hybrid Element Method For Capacitance Extraction In Vlsi Layout Verification System
, 1996
"... In this paper we describe a hybrid element method which combines the boundary element method (BEM) and the finite element method (FEM) to calculate circuit models for layout dependent capacitances. The method can handle irregularities in the stratification of the layout of the integrated circuits (I ..."
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In this paper we describe a hybrid element method which combines the boundary element method (BEM) and the finite element method (FEM) to calculate circuit models for layout dependent capacitances. The method can handle irregularities in the stratification of the layout of the integrated circuits (IC's). We present a standalone extraction program which we developed for validation and testing purposes. We show that the hybrid method can be included in our VLSI layout verification package Space. 1 Introduction Parasitic interconnect capacitances in integrated circuits (IC's) are playing an increasingly significant role in the circuit's performance. Therefore, designers of modern IC's rely heavily on layouttocircuit extraction systems, which produce an equivalent electrical model from the layout. Subsequent simulation verifies correct behavior of the circuit before costly fabrication. Until now, the BEM (Brebbia [2], Ruehli [5], Dewilde [3]) was one of the most popular techniques empl...