Abstract—This paper presents a physical model for planar spiral inductors on silicon, which accounts for eddy current effect in the conductor, crossover capacitance between the spiral and center-tap, capacitance between the spiral and substrate, substrate ohmic loss, and substrate capacitance. The model has been confirmed with measured results of inductors having a wide range of layout and process parameters. This scalable inductor model enables the prediction and optimization of inductor performance. Index Terms—Eddy currents, inductor model, on-chip inductors, quality factor, self resonance, substrate loss. I.

The design and optimization of spiral inductors on silicon substrates, the related layout issues in integrated circuits, and the effect of the inductor-Q on the performance of radiofrequency (RF) building blocks are discussed. Integrated spiral inductors with inductances of 0.5--100 nH and Q's up to 40 are shown to be feasible in very-large-scale-integration silicon technology. Circuit design aspects, such as a minimum inductor area, the cross talk between inductors, and the effect of a substrate contact on the inductor characteristics are addressed. Important RF building blocks, such as a bandpass filter, low-noise amplifier, and voltage-controlled oscillator are shown to benefit substantially from an improved inductor-Q.

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This paper presents a novel RF IC varactor implemented in standard CMOS process. This device has shown a remarkable tuning range of 150#, sensitivity of 300##V, and quality factor of 23 at 1 GHz. A physical model of the varactor is presented and con#rmed with measured data. Using the model derived, optimization has shown that a Q as high as 200 can be achieved. I. Introduction High quality on-chip varactors are essential to monolithic integration of voltage-controlled oscillators in a Si-based RF ICs. Conventionally, on-chip varactors have been implemented with pn junctions under reverse bias or MOS capacitors in depletion-inversion regime. PN-junction varactors have been reported with quality factor #Q# of less than 7 for capacitance of 1#10 pF at 0.9#2.4 GHz. Typical MOS capacitors can achieve higher Q #14#GHz#pF# with larger capacitance per area #1#. In this paper, we presentanovel varactor based on an NMOS-like structure biased in accumulation-depletion regime. A physical model i...

This paper reports L-band and C-band monolithic low noise amplifiers (LNA) fabricated with MOSFET /SIMOX (Separation by IMplanted OXygen) technology for the first time. The L-band LNA exhibits a Gain/(PdcNF) ratio of 0.7/mW, which demonstrate the potential performance advantage of this technology. The C-band LNA has 0.05/mW at 5.8 GHz. The L-band amplifier had a gain of 8.5 dB at 0.5 V, which is the lowest supply voltage ever reported in Si-based LNAs. These LNAs consist of 0.25-m nMOSFET/SIMOX, spiral inductors, and capacitors which are fabricated with a conventional digital CMOS LSI process. It demonstrates that L- and C-band RF circuits can be made on a SIMOX wafer together with large-scale digital circuits.