Abstract — This paper proposes a new approach to multilevel logic optimization based on automatic test pattern generation (ATPG). It shows that an ordinary test generator for single stuckat faults can be used to perform arbitrary transformations in a combinational circuit and discusses how this approach relates to conventional multilevel minimization techniques based on Boolean division. Furthermore, effective heuristics are presented to decide what network manipulations are promising for minimizing the circuit. By identifying indirect implications between signals in the circuit, transformations can be derived which are “good ” candidates for the minimization of the circuit. A main advantage of the proposed approach is that it operates directly on the structural netlist description of the circuit so that the technical consequences of the performed transformations can be evaluated in an easy way, permitting better control of the optimization process with respect to the specific goals of the designer. Therefore, the presented technique can serve as a basis for optimization techniques targeting nonconventional design goals. This has already been shown for random pattern testability [11] and low-power consumption [28]. This paper only considers area minimization, and our experimental results show that the method presented is competitive with conventional technologyindependent minimization techniques. For many benchmark circuits, our tool Hannover implication tool based on learning (HANNIBAL) achieves the best minimization results published to date. Furthermore, the optimization approach presented is shown to be useful in formal verification. Experimental results show that our optimization-based verification technique works robustly for practical verification problems on industrial designs. Index Terms—ATPG, implication analysis, logic synthesis, logic verification, miter, permissible function, recursive learning, redundancy elimination, transduction. I.

This paper presents a technique to determine prime implicants in multi-level combinational networks. The method is based on a graph representation of Boolean functions called AND/OR reasoning graphs. This representation follows from a search strategy to solve the satisfiability problem that is radically different from conventional search for this purpose (such as exhaustive simulation, backtracking, BDDs). The paper shows how to build AND/OR reasoning graphs for arbitrary combinational circuits and proves basic theoretical properties of the graphs. It will be demonstrated that AND/OR reasoning graphs allow us to naturally extend basic notions of two-level switching circuit theory to multi-level circuits. In particular, the notions of prime implicants and permissible prime implicants are defined for multi-level circuits and it is proved that AND/OR reasoning graphs represent all these implicants. Experimental results are shown for PLA factorization. 1 Introduction This paper presents a...

In this paper we present a new model for diagnosis of errors in Synchronous Sequential Circuits (SCC) on the functional level. In contrast to many previously published approaches we do not consider a specific implementation. Instead we use tests based on the transition behavior of the corresponding Finite State Machine (FSM). Thus, the approach can be used for verification and test. We describe a method for constructing a minimal cost test based on AND/OR graphs. Exact and heuristic methods are presented. First experimental results for randomly generated FSMs are given that demonstrate the efficiency of our approach. 1 Introduction Nowadays, circuit design is becoming more and more complex. Thus, the error probability also increases. Since time-to-market aspects are increasingly important it is desirable to detect errors as early as possible. Additionally, this also reduces the production costs. For this, nowadays CAD tools should also support features for error diagnosis, i.e. error...

A new methodology for formal logic verification of combinational circuits is presented. Specifically, a structural approach is used, based on indirect implications derived by recursive learning. It is shown that implications can be used to capture similarity between designs. This is extended to formulate a hybrid approach, this structural information is used to reduce the complexity of a subsequent functional method based on OBDDs. We demonstrate that OBDD-based verification can take great advantage of structural preprocessing in a synthesis environment where many small operations are performed that modify the circuit. The experimental results show that an effective combination can be achieved between memory efficient structural methods and powerful functional methods.