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159
FastHenry: A MultipoleAccelerated 3D Inductance Extraction Program
, 1994
"... tion based on mesh analysis can be combined with a GMRESstyle iterative matrix solution technique to make a reasonably fast 3D frequency dependent inductance and resistance extraction algorithm. Unfortunately, both the computation time and memory re quired for that approach grow faster than n 2, ..."
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Cited by 179 (38 self)
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tion based on mesh analysis can be combined with a GMRESstyle iterative matrix solution technique to make a reasonably fast 3D frequency dependent inductance and resistance extraction algorithm. Unfortunately, both the computation time and memory re quired for that approach grow faster than n 2, where n is the number of volumefilaments. In this paper, we show that it is possible to use multipoleacceleration to reduce both required memory and computation time to nearly order n. Results from examples are given to demonstrate that the multipole acceleration can reduce required computation time and memory by more than an order of magnitude for realistic packaging problems.
A PrecorrectedFFT Method for Electrostatic Analysis of Complicated 3D Structures
 IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems
, 1997
"... In this paper we present a new algorithm for accelerating the potential calculation which occurs in the inner loop of iterative algorithms for solving electromagnetic boundary integral equations. Such integral equations arise, for example, in the extraction of coupling capacitances in threedimensio ..."
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Cited by 70 (26 self)
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In this paper we present a new algorithm for accelerating the potential calculation which occurs in the inner loop of iterative algorithms for solving electromagnetic boundary integral equations. Such integral equations arise, for example, in the extraction of coupling capacitances in threedimensional (3D) geometries. We present extensive experimental comparisons with the capacitance extraction code FASTCAP [1] and demonstrate that, for a wide variety of geometries commonly encountered in integrated circuit packaging, onchip interconnect and microelectromechanical systems, the new "precorrectedFFT " algorithm is superior to the fast multipole algorithm used in FASTCAP in terms of execution time and memory use. At engineering accuracies, in terms of a speedmemory product, the new algorithm can be superior to the fast multipole based schemes by more than an order of magnitude.
Interconnect design for deep submicron ICs
 IN PROC. INT. CONF. ON COMPUTER AIDED DESIGN
, 1997
"... Interconnect has become the dominating factor in determining circuit performance and reliability in deep submicron designs. In this embedded tutorial, we first discuss the trends and challenges of interconnect design as the technology feature size rapidly decreases towards below 0.1 micron. Then, we ..."
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Cited by 68 (22 self)
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Interconnect has become the dominating factor in determining circuit performance and reliability in deep submicron designs. In this embedded tutorial, we first discuss the trends and challenges of interconnect design as the technology feature size rapidly decreases towards below 0.1 micron. Then, we present commonly used interconnect models and a set of interconnect design and optimization techniques for improving interconnect performance and reliability. Finally, we present comparisons of different optimization techniques in terms of their efficiency and optimization results, and show the impact of these optimization techniques on interconnect performance in each technology generation from the 0.35µm to 0.07µm projected in the National Technology Roadmap for Semiconductors.
A ThermallyAware Performance Analysis of Vertically Integrated (3D) ProcessorMemory Hierarchy
 In Proceedings of DAC43
, 2006
"... Threedimensional (3D) integrated circuits have emerged as promising candidates to overcome the interconnect bottlenecks of nanometer scale designs. While they offer several other advantages, it is expected that the benefits from this technology can potentially be offset by thermal considerations ..."
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Cited by 34 (6 self)
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Threedimensional (3D) integrated circuits have emerged as promising candidates to overcome the interconnect bottlenecks of nanometer scale designs. While they offer several other advantages, it is expected that the benefits from this technology can potentially be offset by thermal considerations which impact chip performance and reliability. The work presented in this paper is the first attempt to study the performance benefits of 3D technology under the influence of such thermal constraints. Using a processorcachememory system and carefully chosen applications encompassing different memory behaviors, the performance of 3D architecture is compared with a conventional planar (2D) design. It is found that the substantial increase in memory bus frequency and bus width contribute to a significant reduction in execution time with a 3D design. It is also found that increasing the clock frequency translates into larger gains in system performance with 3D designs than for planar 2D designs in memory intensive applications. The thermal profile of the vertically stacked chip is generated taking into account the highly temperature sensitive leakage power dissipation. The maximum allowed operating frequency imposed by temperature constraint is shown to be lower for 3D than for 2D designs. In spite of these constraints, it is shown that the 3D system registers large performance improvement for memory intensive applications.
A Fast Hierarchical Algorithm for 3D Capacitance Extraction
, 1998
"... We present a new algorithm for computing the capacitance of threedimensional perfect electrical conductors of complex structures. The new algorithm is significantly faster and uses much less memory than previous best algorithms, and is kernel independent. The new algorithm is based on a hierarchic ..."
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Cited by 31 (5 self)
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We present a new algorithm for computing the capacitance of threedimensional perfect electrical conductors of complex structures. The new algorithm is significantly faster and uses much less memory than previous best algorithms, and is kernel independent. The new algorithm is based on a hierarchical algorithm for the nbody problem, and is an acceleration of the boundaryelement method for solving the integral equation associated with the capacitance extraction problem. The algorithm first adaptively subdivides the conductor surfaces into panels according to an estimation of the potential coefficients and a usersupplied error bound. The algorithm stores the potential coefficient matrix in a hierarchical data structure of size O#n#, although the matrix is size n 2 if expanded explicitly, where n is the number of panels. The hierarchical data structure allows us to multiply the coefficient matrix with any vector in O#n# time. Finally, we use a generalized minimal residual algorithm to solve...
MultipoleAccelerated Capacitance Extraction Algorithms for 3D Structures with Multiple Dielectrics
 IEEE Transactions on Circuits and Systems
, 1992
"... This paper describes how to extend the multipoleaccelerated boundaryelement method lbr 3D capacitance com putation to the case where conductors are embedded in an arbitrary piecewiseconstant dielectric medium. Results are pre sented to demonstrate that the method is accurate, has nearly linear ..."
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Cited by 24 (6 self)
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This paper describes how to extend the multipoleaccelerated boundaryelement method lbr 3D capacitance com putation to the case where conductors are embedded in an arbitrary piecewiseconstant dielectric medium. Results are pre sented to demonstrate that the method is accurate, has nearly linear computational growth, and can be nearly two orders of magnitude faster than the standard boundaryelement method based on matrix factorization.
Emerging simulation approaches for micromachined devices
 IEEE Trans. Comput. Aided Design of Integrated Circuits and Systems
"... Abstract—In this survey paper, we describe and contrast three different approaches for extending circuit simulation to include micromachined devices. The most commonly used method, that of using physical insight to develop parameterized macromodels, is presented first. The issues associated with fit ..."
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Cited by 21 (2 self)
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Abstract—In this survey paper, we describe and contrast three different approaches for extending circuit simulation to include micromachined devices. The most commonly used method, that of using physical insight to develop parameterized macromodels, is presented first. The issues associated with fitting the parameters to simulation data while incorporating design attribute dependencies are considered. The numerical model order reduction approach to macromodeling is presented second, and some of the issues associated with fast solvers and model reduction are summarized. Lastly, we describe the recently developed circuitbased approach for simulating micromachined devices, and describe the design hierarchy and the use of a catalog of parts. Index Terms—Extraction, macromodeling, MEMS, micromachining, microsystems, modelorder reduction, simulation.
Analysis and Justification of a Simple, Practical 2 1/2D Capacitance Extraction Methodology
, 1997
"... This paper addresses postrouting capacitance extraction during performancedriven layout. We first show how basic drivers in process technology (planarization and minimum metal density requirements) actually simplify the extraction problem; we do this by proposing and validating five "foundati ..."
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Cited by 19 (15 self)
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This paper addresses postrouting capacitance extraction during performancedriven layout. We first show how basic drivers in process technology (planarization and minimum metal density requirements) actually simplify the extraction problem; we do this by proposing and validating five "foundations" through detailed experiments with a 3D field solver on representative 0.50µm, 0.35µm and 0.18µm process parameters. We then present a simple yet accurate 2 1/2D extraction methodology directly based on the foundations. This methodology has been productized and is being shipped with the Cadence Silicon Ensemble 5.0 product. We conclude that the 2 1/2D approach has sufficient accuracy for current and nearterm process generations.
Simulating the Behavior MEMS Devices: Computational methods and Needs
, 1997
"... classes of pressure sensors, every new MEMS product idea is essentially a research project. During that research project, years can be spent developing prototypes which are then discarded. The result is an unacceptably long product development cycle or unnecessarily conservative design practices. T ..."
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Cited by 15 (1 self)
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classes of pressure sensors, every new MEMS product idea is essentially a research project. During that research project, years can be spent developing prototypes which are then discarded. The result is an unacceptably long product development cycle or unnecessarily conservative design practices. The first step in reducing design time and allowing for aggressive design strategies is to develop simulation tools that will let designers try "what if" experiments in hours instead of months. Several commercial and academic efforts are underway to devise such simulation systems. 27 To provide these tools, three computational challenges are being addressed. First, faster algorithms are being developed for computing surface forces due to fields or fluids exterior to geometrically complex, flexible threedimensional structures. Second, since the performance of most microma Simulating the Behavior of MEMS Devices: Computational Methods and Needs STEPHEN D. SENTURIA, NARAYAN ALURU, AND J
Modeling and Analysis of Differential Signaling for Minimizing Inductive CrossTalk
 DAC
, 2001
"... Many physical synthesis tools interdigitate signal and power lines to reduce crosstalk, and thus, improve signal integrity and timing predictability.Such approaches are extremely effective at reducing crosstalk at circuit speeds where inductive effects are inconsequential. In this paper, we use a ..."
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Cited by 14 (1 self)
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Many physical synthesis tools interdigitate signal and power lines to reduce crosstalk, and thus, improve signal integrity and timing predictability.Such approaches are extremely effective at reducing crosstalk at circuit speeds where inductive effects are inconsequential. In this paper, we use a detailed distributed RLC model to show that inductive crosstalk effects are substantial in long busses associated with 0.18 micron technology. Simulation experiments are then used to demonstrate that crosstalk in such high speed technologies is much better controlled by redeploying interdigitated power lines to perform differential signaling.