At the nanometer scale, the focus of micro-architecture will move from processing to communication. Most general computer architectures to date have been based on a "stored program" paradigm that differentiates between memory and processing and relies on communication over busses and other (relatively) long distance mechanisms. Nanometer-scale electronics -- nanoelectronics - promises to fundamentally change the ground-rules. Processing will be cheap and plentiful, interconnection expensive but pervasive. This will tend to move computer architecture in the direction of locallyconnected, reconfigurable hardware meshes that merge processing and memory. If the overheads associated with reconfigurability can be reduced or even eliminated, architectures based on non-volatile, reconfigurable, finegrained meshes with rich, local interconnect offer a better match to the expected characteristics of future nanoelectronic devices.

This paper provides an overview of research developments toward nanometer-scale electronic switching devices for use in building ultra-densely integrated electronic computers. Specifically, two classes of alternatives to the field-effect transistor are considered: 1) quantum-effect and single-electron solid-state devices and 2) molecular electronic devices. A taxonomy of devices in each class is provided, operational principles are described and compared for the various types of devices, and the literature about each is surveyed. This information is presented in nonmathematical terms intended for a general, technically interested readership

this paper, we will describe some ideas of the Notre Dame NanoDevices Group on a possible future nanoelectronic computing technology based on cells of coupled quantum dots.

Compilation has a long history of translating a programmer’s human-readable code into machine instructions designed to make good use of a specific target computer. In this paper, we formalize a compiler framework that broadly defines the task of compilation to include output of a machine description customized to the input program which would be used to generate the target computer. The compiled program would then run on the generated computer. Inspired by research in design space exploration, this compilation approach exploits the proposed capabilities of nanocomputers, which are in the class of reconfigurable parallel architectures. This emerging hardware technology relies on molecular level fabricated circuit design to minimize feature size while creating a vast matrix of reconfigurable processing units, an application of the advancing field of nanotechnology. We identify design issues and present preliminary results that support earlier work in this area and propose future directions.

In this report, a future scenario concerning the economic direction of the computing industry has been presented. This future scenario was based on past developments within the computing industry. The continued miniaturization of semiconductor components was discussed based on observed trends for transistors. The physical limitations for transistor devices were also addressed. The use of x-ray lithography for the construction of devices on a “nano-scale ” was considered. Next, cost trends within the microelectronics industry were explored. Although the cost per transistor has been observed to decrease, total equipment costs and facilities costs were observed to rise. Trend extrapolation was next used to predict the future cost per transistor and the number of transistors per chip. By taking the product of these two predicted quantities, an equation for the future manufacturing cost per chip was determined. A parametric cost estimation model (VHSIC Model) for the prediction of avionics computer system costs was modified to reflect the future performance parameters of nanoelectronics. Using data from the x86 design of Intel ® Microprocessor Chips, undetermined parameters of the Modified VHSIC Model were calculated. Next, future performance parameters were used in the model to predict the initial selling price of future chips. The resulting predictions from this model indicated that chip prices are expected to increase while the price per electronic function will decrease. Finally, profit-time models for semiconductor chips and transistors were derived. These models were used to predict the future profit for a chip or transistor.

For the past 40 years, since the invention of the integrated circuit, the number of transistors on a computer chip has doubled roughly every 18 months. As the limits of photolithography are rapidly approached, however, it is becoming clear that continued increases in circuit density will require fairly dramatic changes in the way transistors are designed and operated. This review summarizes current strategies for fabricating transistors which operate based on the flow of single electrons through nanometre-sized metal and semiconductor particles; i.e. single electron transistors (SETs). Because the room temperature operation of SETs requires nanoparticles < 10 nm in diameter, we focus mainly on devices which have the potential for being assembled from the solution phase (non-lithographic systems). Several applications of SETs are discussed in addition to the major hurdles which must be overcome for their implementation in electronic device technology. 1

This paper surveys and explains nanometer-scale, quantum-effect alternatives to micron-scale, bulk-effect transistors in digital circuits. The status of R&D and recent important advances are reviewed briefly.