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Using Typed Lambda Calculus to Implement Formal Systems on a Machine
 Journal of Automated Reasoning
, 1992
"... this paper and the LF. In particular the idea of having an operator T : Prop ! Type appears already in De Bruijn's earlier work, as does the idea of having several judgements. The paper [24] describes the basic features of the LF. In this paper we are going to provide a broader illustration of its a ..."
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Cited by 83 (14 self)
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this paper and the LF. In particular the idea of having an operator T : Prop ! Type appears already in De Bruijn's earlier work, as does the idea of having several judgements. The paper [24] describes the basic features of the LF. In this paper we are going to provide a broader illustration of its applicability and discuss to what extent it is successful. The analysis (of the formal presentation) of a system carried out through encoding often illuminates the system itself. This paper will also deal with this phenomenon.
Completing the Temporal Picture
, 1991
"... The paper presents a relatively complete proof system for proving the validity of temporal properties of reactive programs. The presented proof system improves on previous temporal systems, in that it reduces the validity of program properties into pure assertional reasoning, not involving additiona ..."
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Cited by 74 (16 self)
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The paper presents a relatively complete proof system for proving the validity of temporal properties of reactive programs. The presented proof system improves on previous temporal systems, in that it reduces the validity of program properties into pure assertional reasoning, not involving additional temporal reasoning. The proof system is based on the classification of temporal properties according to the Borel hierarchy, providing appropriate proof rules for the classes of safety, response, and reactivity properties.
Formal Methods for the Specification and Design of RealTime Safety Critical Systems
, 1992
"... Safety critical computers increasingly a#ect nearly every aspect of our lives. Computers control the planes we #y on, monitor our health in hospitals and do our work in hazardous environments. Computers with software de#ciencies that fail to meet stringent timing constraints have resulted in cat ..."
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Cited by 31 (0 self)
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Safety critical computers increasingly a#ect nearly every aspect of our lives. Computers control the planes we #y on, monitor our health in hospitals and do our work in hazardous environments. Computers with software de#ciencies that fail to meet stringent timing constraints have resulted in catastrophic failures. This paper surveys formal methods for specifying, designing and verifying realtime systems, so as to improve their safety and reliability. # To appear in Journal of Systems and Software,Vol. 18, Number 1, pages 33#60, April 1992. Jonathan Ostro# is with the Department of Computer Science, York University 4700 Keele Street, North York, Ontario, Canada, M3J 1P3. This work is supported by the Natural Sciences and Engineering Research Council of Canada. 1 CONTENTS 2 Contents 1 Introduction 3 2 De#ning the terms 6 2.1 Major issues that formal theories must address ::::::: 13 3 RealTime Programming Languages 14 4 Structured Methods and#or Graphical Languages 15 4.1 Str...
Temporal Logic and Z Specifications
 Australian Computer Journal
, 1989
"... The Z specification language can be used to capture liveness properties of state transition systems such as those used to specify communications protocols. The specification of such systems involve temporal concepts such as "eventually" and "always". In this paper we extend standard Z to include the ..."
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Cited by 11 (0 self)
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The Z specification language can be used to capture liveness properties of state transition systems such as those used to specify communications protocols. The specification of such systems involve temporal concepts such as "eventually" and "always". In this paper we extend standard Z to include the temporal logic operators so as to provide a powerful notation for discussing the liveness of state transition systems. By way of an illustration of the ideas involved, we look at a state transition model for an alternating bit protocol, and compare the specifications of liveness in standard Z and Z enhanced with the temporal logic notation. Keywords and Phrases : liveness, protocols, temporal logic, Z CR Categories : c.2.2, d.2.1, d.2.4, f.3.1 1 Introduction In Duke et al [2, 3] the Z specification language [7, 10] was used to model communications protocols as eventdriven [9] state transition systems [11]. The Z language, developed at the Programming Research Group of Oxford University ...
Bounded Fairness
 Verification: Theory and Practice
, 1993
"... Bounded fairness, a stronger notion than the usual fairness based on eventuality, can be used, for example, to relate the frequency of shared resource access of a particular process with regard to other processes that access the resource with mutual exclusion. We formalize bounded fairness byintrod ..."
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Cited by 11 (0 self)
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Bounded fairness, a stronger notion than the usual fairness based on eventuality, can be used, for example, to relate the frequency of shared resource access of a particular process with regard to other processes that access the resource with mutual exclusion. We formalize bounded fairness byintroducing a new binary operator into temporal logic. One main di#erence between this logic and explicittime logics, one whichwe consider to be an advantage in many cases, is that time does not appear explicitly as a parameter. The syntax and semantics for this new logic,kTL,aregiven. This logic is shown to be more powerful than temporal logic with the eventualityoperator and as powerful as the logic with the until operator. We argue that kTL can be used to specify bounded fairness requirements in a more natural manner than is possible with until; in particular, we show properties that can be expressed more succinctly in kTL. We also give a procedure for testing satis#abilityofkTL formulas. A...
Ground Temporal Logic: A Logic for Hardware Verification
 ComputerAided Verification (CAV '94), LNCS 818
, 1994
"... We present a new temporal logic, GTL, appropriate for specifying properties of hardware at the register transfer level. We argue that this logic represents an improvement over model checking for some natural hardware verification problems. We show that the validity problem for this logic is \Pi 1 1 ..."
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Cited by 7 (0 self)
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We present a new temporal logic, GTL, appropriate for specifying properties of hardware at the register transfer level. We argue that this logic represents an improvement over model checking for some natural hardware verification problems. We show that the validity problem for this logic is \Pi 1 1 complete. We then identify a fragment of the logic that is decidable. We show that in this fragment we are still able to encode many interesting problems, including the correctness of pipelined microprocessors. 1 Introduction Temporal logic is a natural logic for hardware verification. Specifically model checking for various propositional temporal logics has proven to be a very practical tool for the fully automatic verification of many hardware circuits and finite state protocols. However these approaches suffer from various drawbacks. One such drawback is the requirement that hardware implementations be carried out to the bitlevel. This can lead to the state explosion problem as the numb...
Control Path Oriented Verification of Sequential Generic Circuits with Control and Data Path
 In Proceeding of the European Design and Test Conference
, 1994
"... Usually, digital circuits are split up into control and data path as there are specific synthesis methods for controllers and operation units. However, all known approaches to hardware verification which make use of this fact, model the operation unit also as a finitestate machine. This leads to en ..."
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Cited by 3 (2 self)
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Usually, digital circuits are split up into control and data path as there are specific synthesis methods for controllers and operation units. However, all known approaches to hardware verification which make use of this fact, model the operation unit also as a finitestate machine. This leads to enormous space requirements which limit the applicability of these approaches. In order to avoid this, abstraction mechanisms can be used to map boolean tuples onto more complex data types. However, approaches to the verification of generic nbit circuits have considered so far only circuits with simple controllers, such that the verification of only combinational circuits or special cases of sequential circuits is possible. In this paper, we present a new approach to hardware verification which allows the verification of generic circuits with nontrivial controllers. 1 Introduction Over the last few years, a lot of formal approaches to hardware verification have been developed, e.g. equival...
Modeling Interaction by Sheaves and Geometric Logic
 In G. Ciobanu and Gh. Paun eds, Proc. International Conference Fundamentals of Computation Theory (FCT’99), LNCS 1684
, 1999
"... In this paper we show that, given a family of interacting systems, many notions which are important for expressing properties of systems can be modeled as sheaves over a suitable topological space. ..."
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Cited by 3 (1 self)
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In this paper we show that, given a family of interacting systems, many notions which are important for expressing properties of systems can be modeled as sheaves over a suitable topological space.
A complete temporal and spatial logic for distributed systems
 In Frontiers of Combining Systems (FroCoS), volume 3717 of LNAI
, 2005
"... Abstract. In this paper, we introduce a spatial and temporal logic for reasoning about distributed computation. The logic is a combination of an extension of hybrid logic, that allows us to reason about the spatial structure of a computation, and linear temporal logic, which accounts for the tempora ..."
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Cited by 1 (0 self)
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Abstract. In this paper, we introduce a spatial and temporal logic for reasoning about distributed computation. The logic is a combination of an extension of hybrid logic, that allows us to reason about the spatial structure of a computation, and linear temporal logic, which accounts for the temporal aspects. On the pragmatic side, we show the wide applicability of this logic by means of many examples. Our main technical contribution is completeness of the logic both with respect to spatial/temporal structures and a class of spatial transition systems. 1
The Correctness of the PACLIB Kernel  A Case Study in Parallel Program Verification by Temporal Logic
, 1993
"... We verify the correct implementation of a nondeterministic construct for the delivery of task results in the parallel computer algebra library Paclib. First we explain the corresponding part of the Paclib runtime kernel. Then we give an overview on the calculus of temporal logic and extend it for o ..."
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Cited by 1 (1 self)
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We verify the correct implementation of a nondeterministic construct for the delivery of task results in the parallel computer algebra library Paclib. First we explain the corresponding part of the Paclib runtime kernel. Then we give an overview on the calculus of temporal logic and extend it for our purposes. We describe how the Paclib kernel is modelled in this formal framework. We formulate several key theorems and auxiliary lemmas that capture the dynamic behavior of the construct and verify their correctness. Based on the experiences of this case study, we describe some general verification strategies. Supported by the FWF grant S5302PHY "Parallel Symbolic Computation". 2 CONTENTS Contents 1 Introduction 4 2 Parallel Program Verification 5 2.1 Organization of the Verification : : : : : : : : : : : : : : : : : : : : : : : : : 5 2.2 Program Model and Implementation : : : : : : : : : : : : : : : : : : : : : : 6 2.3 The Complexity of Verification : : : : : : : : : : : : : : :...