This paper investigates threshold based neural networks for periodic symmetric Boolean functions and some related operations. It is shown that any n-input variable periodic symmetric Boolean function can be implemented with a feed-forward linear threshold based neural network with size of O(log n) and depth also of O(log n), both measured in terms of neurons. The maximum weight and fan-in values are in the order of O(n). Under the same assumptions on weight and fan-in values, an asymptotic bound of O(log n) for both size and depth of the network is also derived for symmetric Boolean functions that can be decomposed into a constant number of periodic symmetric Boolean sub-functions. Based on this results neural networks for serial binary addition and multiplication of n-bit operands are also proposed. It is shown that the serial addition can be computed with polynomially bounded weights and a maximum fan-in in the order of O(log n) in O( n log n ) serial cycles, where a serial cycle c...

This paper demonstrates the advantages of using online arithmetic for traditional and advanced detection algorithms for communication systems. Detection is one of the core computationally-intensive physical layer operations in a communication receiver and determines the communication data rates. Detection algorithms typically involve hard decisions (sign based testing) to find the sign of the transmitted information bit. This results in extraneous computations in a conventional number system as the sign is obtained only at the end due to the Least Significant Digit First (LSDF) nature of computations. On-line arithmetic, based on a signed digit number representation, provides Most Significant Digit First (MSDF) computation. Hence, the computations can stop after the first non-zero MSD (sign) is computed and additional computations for the successive digits can be avoided. Back-conversion to a conventional number system is not required as the sign of the digit represents the detected bit. A comparison of a radix-4 serial digit on-line multiuser detector with an 8-bit parallel conventional arithmetic multiuser detector shows a decrease in latency by 1.79X, a 3X increase in throughput, and possible savings in area.

This report describes the DITPOS algorithm from specifications to implementation. DITPOS is used as noise-robust preprocessor for feature extraction from speech signals as part of an automatic speech recognition system. The DITPOS algorithm is based upon application of SVD, the novel defined direction weighted total least squares solution and a criterion for selecting the parsimonious-order individually for each frame of the speech signal. Simulation experiments carried out show that DITPOS performs significantly better than the standard Levinson approach then the speech signals are contaminated with additive white noise. Next, the derivation of a VLSI suited architecture with minimal area consumption for given timing constraints is considered. Emphasis is devoted to the design script for performing architecture synthesis as well as the actual architecture synthesis. The design script applied, Architect, is based on formal methods for doing scheduling and heuristics for doing allocatio...