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22
Microprocessor Design Verification
 Journal of Automated Reasoning
, 1989
"... The verification of a microprocessor design has been accomplished using a mechanical theorem prover. This microprocessor, the FM8502, is a 32bit general purpose, von Neumann processor whose designlevel (gatelevel) specification has been verified with respect to its instructionlevel specification ..."
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Cited by 59 (3 self)
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The verification of a microprocessor design has been accomplished using a mechanical theorem prover. This microprocessor, the FM8502, is a 32bit general purpose, von Neumann processor whose designlevel (gatelevel) specification has been verified with respect to its instructionlevel specification. Both specifications were written in the BoyerMoore logic, and the proof of correctness was carried out with the BoyerMoore theorem prover.
Experience with embedding hardware description languages in HOL
 Theorem Provers in Circuit Design
, 1992
"... Abstract The semantics of hardware description languages can be represented in higher order logic. This provides a formal definition that is suitable for machine processing. Experiments are in progress at Cambridge to see whether this method can be the basis of practical tools based on the HOL theor ..."
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Cited by 39 (4 self)
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Abstract The semantics of hardware description languages can be represented in higher order logic. This provides a formal definition that is suitable for machine processing. Experiments are in progress at Cambridge to see whether this method can be the basis of practical tools based on the HOL theoremproving assistant. Three languages are being investigated: ELLA, Silage and VHDL. The approaches taken for these languages are compared and current progress on building semanticallybased theoremproving tools is discussed.
A mechanically verified code generator
 Journal of Automated Reasoning
, 1989
"... in this document are those of the author and should not be interpreted as representing the official policies, either expressed or implied, of Computational ..."
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Cited by 31 (1 self)
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in this document are those of the author and should not be interpreted as representing the official policies, either expressed or implied, of Computational
Hardware Verification using Monadic SecondOrder Logic
 IN COMPUTER AIDED VERIFICATION : 7TH INTERNATIONAL CONFERENCE, CAV '95, LNCS 939
, 1995
"... We show how the secondorder monadic theory of strings can be used to specify hardware components and their behavior. This logic admits a decision procedure and countermodel generator based on canonical automata for formulas. We have used a system implementing these concepts to verify, or find e ..."
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Cited by 25 (10 self)
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We show how the secondorder monadic theory of strings can be used to specify hardware components and their behavior. This logic admits a decision procedure and countermodel generator based on canonical automata for formulas. We have used a system implementing these concepts to verify, or find errors in, a number of circuits proposed in the literature. The techniques we use make it easier to identify regularity in circuits, including those that are parameterized or have parameterized behavioral specifications. Our proofs are semantic and do not require lemmas or induction as would be needed when employing a conventional theory of strings as a recursive data type.
DILL: Specifying Digital Logic in LOTOS
, 1994
"... Data Type) operations on input values. However, the timedependent behaviour of logic circuits is often important, so it is better to use LOTOS behaviour expressions. More importantly, a specification using ADTs would not readily support `wiring up' a circuit. Each logic gate is therefore specified ..."
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Cited by 21 (17 self)
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Data Type) operations on input values. However, the timedependent behaviour of logic circuits is often important, so it is better to use LOTOS behaviour expressions. More importantly, a specification using ADTs would not readily support `wiring up' a circuit. Each logic gate is therefore specified as a LOTOS process, instantiated with appropriate parameters. A real logic gate exhibits a propagation delay from a change in input to the subsequent output. This appears naturally in a LOTOS specification since output events follow input events. However, the actual time delay between such events is not modelled in LOTOS. For many purposes the exact delay is unimportant, since a design that assumed specific propagation delays in each real gate might be prone to race conditions. Many logic designs are synchronous to 2 Since `gate' has both a hardware meaning and a LOTOS meaning, the term is qualified where necessary. avoid such problems, and this removes the need to model delays explicitl...
Using Recursive Types to Reason about Hardware in Higher Order Logic
, 1988
"... : The expressive power of higher order logic makes it possible to define a wide variety of data types within the logic and to prove theorems that state the properties of these types concisely and abstractly. This paper describes how such defined data types can be used to support formal reasoning in ..."
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Cited by 19 (1 self)
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: The expressive power of higher order logic makes it possible to define a wide variety of data types within the logic and to prove theorems that state the properties of these types concisely and abstractly. This paper describes how such defined data types can be used to support formal reasoning in higher order logic about the behaviour of hardware designs. First printed: May 1988 Reprinted with revisions: April 1990 An earlier version of this paper appears in: The Fusion of Hardware Design and Verification, ed. G.J. Milne (NorthHolland, 1988), pp. 2750. Contents Introduction 5 1 Hardware Verification using Higher Order Logic 5 1.1 Notation : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 5 1.2 Specifying Hardware Behaviour : : : : : : : : : : : : : : : : : : 6 1.3 Specifying Hardware Structure : : : : : : : : : : : : : : : : : : 7 1.4 Formulating Correctness : : : : : : : : : : : : : : : : : : : : : : 8 2 Recursive Types in Higher Order Logic 8 2.1 Type Definit...
A Correctness Model for Pipelined Microprocessors
"... What does it mean for an instruction pipeline to be correct? We recently completed the specification and verification of a pipelined microprocessor called Uinta. Our proof makes no simplifying assumptions about data and control hazards. This paper presents the specification, describes the verific ..."
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Cited by 18 (1 self)
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What does it mean for an instruction pipeline to be correct? We recently completed the specification and verification of a pipelined microprocessor called Uinta. Our proof makes no simplifying assumptions about data and control hazards. This paper presents the specification, describes the verification, and discusses the effect of pipelining on the correctness model. 1 Introduction Much has been written over the years regarding the formal specification and verification of microprocessors. Most of these efforts have been directed at nonpipelined microprocessors [Gor83, Bow87, Hun87, CCLO88, Coh88, Joy88, Hun89, Win90, Her92, SWL93, Win94b]. The verification of pipelined microprocessors presents unique challenges. The correctness model is somewhat different than the standard correctness models used previously (see Section 7.1). Besides the correctness model, the concurrent operations inherent in a pipeline lead to hazards which must be considered in the proof. There are three typ...
Automata Based Symbolic Reasoning in Hardware Verification
, 1998
"... . We present a new approach to hardware verification based on describing circuits in Monadic Secondorder Logic (M2L). We show how to use this logic to represent generic designs like nbit adders, which are parameterized in space, and sequential circuits, where time is an unbounded parameter. M2L ad ..."
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Cited by 18 (11 self)
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. We present a new approach to hardware verification based on describing circuits in Monadic Secondorder Logic (M2L). We show how to use this logic to represent generic designs like nbit adders, which are parameterized in space, and sequential circuits, where time is an unbounded parameter. M2L admits a decision procedure, implemented in the Mona tool [17], which reduces formulas to canonical automata. The decision problem for M2L is nonelementary decidable and thus unlikely to be usable in practice. However, we have used Mona to automatically verify, or find errors in, a number of circuits studied in the literature. Previously published machine proofs of the same circuits are based on deduction and may involve substantial interaction with the user. Moreover, our approach is orders of magnitude faster for the examples considered. We show why the underlying computations are feasible and how our use of Mona generalizes standard BDDbased hardware reasoning. 1. Introduction Correctnes...
Implementing a Methodology for Formally Verifying RISC Processors in HOL
, 1994
"... . In this paper a methodology for verifying RISC cores is presented. This methodology is based on a hierarchical model of interpreters. This model allows us to define formal specifications at each level of abstraction and successively prove the correctness between the neighbouring abstraction levels ..."
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Cited by 15 (7 self)
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. In this paper a methodology for verifying RISC cores is presented. This methodology is based on a hierarchical model of interpreters. This model allows us to define formal specifications at each level of abstraction and successively prove the correctness between the neighbouring abstraction levels, so that the overall specification is correct with respect to its hardware implementation. The correctness proofs have been split into two steps so that the parallelism in the execution due to the pipelining of instructions, is accounted for. The first step shows that the instructions are correctly processed by the pipeline and the second step shows that the semantic of each instruction is correct. We have implemented the specification of the entire model and performed parts of the proofs in HOL. 1 Introduction Completely automating the verification of general complex systems is practically impossible. Hence appropriate heuristics for specific classes of circuits such as finite state machi...
A Theory of Generic Interpreters
, 1993
"... We present an abstract theory of interpreters. Interpreters are models of computation that are specifically designed for use as templates in computer system specification and verification. The generic interpreter theory contains an abstract representation which serves as an interface to the theory a ..."
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Cited by 13 (3 self)
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We present an abstract theory of interpreters. Interpreters are models of computation that are specifically designed for use as templates in computer system specification and verification. The generic interpreter theory contains an abstract representation which serves as an interface to the theory and as a guide to specification. A set of theory obligations ensure that the theory is being used correctly and provide a guide to system verification. The generic interpreter theory provides a methodology for deriving important definitions and lemmas that were previously obtained in a largely ad hoc fashion. Many of the complex data and temporal abstractions are done in the abstract theory and need not be redone when the theory is used.