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Experience with embedding hardware description languages in HOL
 Theorem Provers in Circuit Design
, 1992
"... Abstract The semantics of hardware description languages can be represented in higher order logic. This provides a formal definition that is suitable for machine processing. Experiments are in progress at Cambridge to see whether this method can be the basis of practical tools based on the HOL theor ..."
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Abstract The semantics of hardware description languages can be represented in higher order logic. This provides a formal definition that is suitable for machine processing. Experiments are in progress at Cambridge to see whether this method can be the basis of practical tools based on the HOL theoremproving assistant. Three languages are being investigated: ELLA, Silage and VHDL. The approaches taken for these languages are compared and current progress on building semanticallybased theoremproving tools is discussed.
Structuring and Automating Hardware Proofs in a HigherOrder TheoremProving Environment
 Formal Methods in System Design
, 1993
"... . In this article we present a structured approach to formal hardware verification by modelling circuits at the registertransfer level using a restricted form of higherorder logic. This restricted form of higherorder logic is sufficient for obtaining succinct descriptions of hierarchically design ..."
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. In this article we present a structured approach to formal hardware verification by modelling circuits at the registertransfer level using a restricted form of higherorder logic. This restricted form of higherorder logic is sufficient for obtaining succinct descriptions of hierarchically designed registertransfer circuits. By exploiting the structure of the underlying hardware proofs and limiting the form of descriptions used, we have attained nearly complete automation in proving the equivalences of the specifications and implementations. A hardwarespecific tool called MEPHISTO converts the original goal into a set of simpler subgoals, which are then automatically solved by a generalpurpose, firstorder prover called FAUST. Furthermore, the complete verification framework is being integrated within a commercial VLSI CAD framework. Keywords: hardware verification, higherorder logic 1 Introduction The past decade has witnessed the spiralling of interest within the academic com...
A Functional Approach for Formalizing Regular Hardware Structures
"... An approach for formalizing hardware behaviour is presented which is based on a small functional programming language called primitive ML (PML). Since the basic constructs of PML are simply typed terms, PML lends itself both to simulation and verification. The semantics of PML is formally embe ..."
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An approach for formalizing hardware behaviour is presented which is based on a small functional programming language called primitive ML (PML). Since the basic constructs of PML are simply typed terms, PML lends itself both to simulation and verification. The semantics of PML is formally embedded in higherorder logic. The formalization
An Overview of the Formal Specification and Verification of the FM9001 Microprocessor
, 1994
"... This document presents the details of the FM9001 development, its specification, and its verification. 1 RESULTS ..."
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This document presents the details of the FM9001 development, its specification, and its verification. 1 RESULTS
A Process Algebra Foundation for Reasoning about Core ELLA
, 1994
"... A process algebraic foundation is developed, for formal analysis of synchronous hardware designs using the commercially available hardware design language, ELLA. An underlying semantic foundation, based on input/outputtrace sets, is presented first through the use of state machines. Such a represent ..."
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A process algebraic foundation is developed, for formal analysis of synchronous hardware designs using the commercially available hardware design language, ELLA. An underlying semantic foundation, based on input/outputtrace sets, is presented first through the use of state machines. Such a representation enables direct application of standard, fully automated, trace equivalence checking tools. However, to overcome the computational limitations imposed by such analysis methods, the input/output trace semantics is represented through a synchronous process algebra, EPA. Primitive processes in EPA denote the behaviour of primitive hardware components, such as delays or multiplexers, with composition operators corresponding to the different ways in which behaviours may be built. Of particular significance is the parallel composition operator which captures the machinery for building networks from other components/networks. Actions in EPA are structured and signify the state of input and ou...
First Steps Towards Automating Hardware Proofs in HOL (Extended Abstract)
, 1991
"... ) Ramayya Kumar, Thomas Kropf, Klaus Schneider University of Karlsruhe, Institute of Computer Design and Fault Tolerance (Prof. Dr. ##. Schmid) P.O. Box 6980, W7500 Karlsruhe, Germany 1. INTRODUCTION The use of higherorder logic and an associated interactive theorem proving environment for hardwar ..."
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) Ramayya Kumar, Thomas Kropf, Klaus Schneider University of Karlsruhe, Institute of Computer Design and Fault Tolerance (Prof. Dr. ##. Schmid) P.O. Box 6980, W7500 Karlsruhe, Germany 1. INTRODUCTION The use of higherorder logic and an associated interactive theorem proving environment for hardware verification has established itself as an important technique for formal hardware validation [CaGM 86, FFFH 89]. In spite of the fact that such techniques are powerful and can be used for validation of complex systems, they continue to remain purely within the purview of theorem proving specialists. The only way to bring such a system closer to circuit designers is to augment the degree of automation and provide a camouflaged environment which mirrors the designer's view of hardware. The first step in this direction is to automate the proofs of all firstorder and simple higherorder statements, within such systems, which has been achieved by the tool FAUST [KuKS 91, ScKK 91a]. Further aut...
Operational Semantics Based Formal Symbolic Simulation
, 1992
"... This paper describes the development of progressively more powerful and abstract hardware simulators. A small computer hardware design and description language picoella is then introduced, followed by its formal semantics. Using a number of small examples, we will then show the how this formal seman ..."
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This paper describes the development of progressively more powerful and abstract hardware simulators. A small computer hardware design and description language picoella is then introduced, followed by its formal semantics. Using a number of small examples, we will then show the how this formal semantics may be used within a proof system as a sophisticated simulation tool. Examples include some full adders, a general N bit adder, and two parity checkers. Keyword Codes: I.2.3; B.7.2; F.3 Keywords: Deduction and Theorem Proving; Integrated Circuits, Design Aids; Logics and Meaning of Programs 1 Introduction This introduction describes the development of various kinds of hardware simulators. Following this, a small hdl called picoella, is introduced in section 2. Its formal semantics, and a brief account of this semantics' embedding in a proof system are described in section 3. Section 4 illustrates the use of the semantics in the capacity of a symbolic simulator, as described in the rema...
The State Evolution Method for Verifying Hardware Systems
, 1995
"... We present a novel state evolution method for establishing standard (strong) bisimulation, which gives a tractable verification approach for deterministic machines, possibly with infinite statespaces, and operates at an abstract level. The problem of establishing equivalence is reduced to one of ..."
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We present a novel state evolution method for establishing standard (strong) bisimulation, which gives a tractable verification approach for deterministic machines, possibly with infinite statespaces, and operates at an abstract level. The problem of establishing equivalence is reduced to one of proving the validity of a set of simpler (firstorder) logical verification conditions, generated from the state evolution expressions. The approach maintains a high degree of automation, a feature of statebased methods, whilst offering the potential of containing the usual growth in complexity of verification, one advantage of using theoremproving techniques. Keywords: symbolic verification, automatic hardware verification, theoremproving, hardware design aids. 1 Introduction One approach commonly used for establishing the behavioural equivalence of hardware systems uses statespace exploration to establish a bisimulation relation between the systems, modelled as labelled transit...
Formal Specification of Programming Languages: A Panoramic
"... ion Mechanisms for Hardware Verification', University of Cambridge Computer Laboratory Technical Report 106, Cambridge, England (May 1987). [30] F.G. Pagan, Formal Specification of Programming Languages: A Panoramic Primer, PrenticeHall, Inc., (1981). [31] D.L. Perry, VHDL, McGrawHill (1991). [ ..."
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ion Mechanisms for Hardware Verification', University of Cambridge Computer Laboratory Technical Report 106, Cambridge, England (May 1987). [30] F.G. Pagan, Formal Specification of Programming Languages: A Panoramic Primer, PrenticeHall, Inc., (1981). [31] D.L. Perry, VHDL, McGrawHill (1991). [32] G. Plotkin, 'A Structural Approach to Operational Semantics', Technical Report DAIMI FN19, Computer Science Dept., rhus University (September 1981). [33] A. Salem and D. Borrione, 'Formal Reasoning About Signal Attributes in VHDL', in proceedings: VHDL Forum for CAD in Europe, Spring 1991 meeting. [34] V. Stavridou, J.A. Goguen, A. Stevens, S.M. Eker, S.N. Aloneftis and K.M. Hobley, 'FUNNEL and 2OBJ: Towards an Integrated Hardware Design Environment', in proceedings: IFIP TC10/WG10.2 International Conference on Theorem Provers in Circuit Designs: Theory, Practice and Experience, edited by V. Stavridou, T. F. Melham and R. T. Boute, NorthHolland, (1992). [35] G. Umbreit, 'Providing a...