Results 11  20
of
193
Estimation of Average Switching Activity in Combinational and Sequential Circuits
 In Proceedings of the 29 th Design Automation Conference
, 1992
"... power dissipated in VLSI combinational and sequential circuits, under random input sequences. Switching activity is strongly affected by gate delays and for this reason we use a general delay model in estimating switching activity. Our method takes into account correlation caused at internal gates i ..."
Abstract

Cited by 103 (9 self)
 Add to MetaCart
power dissipated in VLSI combinational and sequential circuits, under random input sequences. Switching activity is strongly affected by gate delays and for this reason we use a general delay model in estimating switching activity. Our method takes into account correlation caused at internal gates in the circuit due to reconvergence of input signals. In sequential circuits, the input sequence applied to the combinational portion of the circuit is highly correlated because some of the inputs to the combinational logic are flipflop outputs representing the state of the circuit. We present methods to probabilistically estimate switching activity in sequential circuits. These methods automatically compute the switching rates and correlations between flipflop outputs.
Verification of the Futurebus+ Cache Coherence Protocol
, 1995
"... We used a hardware description language to construct a formal model of the cache coherence protocol described in the IEEE Futurebus+ standard. By applying temporal logic model checking techniques, we found errors in the standard. The result of our project is a concise, comprehensible and unambiguous ..."
Abstract

Cited by 103 (16 self)
 Add to MetaCart
We used a hardware description language to construct a formal model of the cache coherence protocol described in the IEEE Futurebus+ standard. By applying temporal logic model checking techniques, we found errors in the standard. The result of our project is a concise, comprehensible and unambiguous model of the protocol that should be useful both to the Futurebus+ Working Group members, who are responsible for the protocol, and to actual designers of Futurebus+ boards.
Markovian Analysis of Large Finite State Machines
 IEEE Transactions on CAD
, 1996
"... Regarding finite state machines as Markov chains facilitates the application of probabilistic methods to very large logic synthesis and formal verification problems. In this paper we present symbolic algorithms to compute the steadystate probabilities for very large finite state machines (up to 10 ..."
Abstract

Cited by 76 (7 self)
 Add to MetaCart
(Show Context)
Regarding finite state machines as Markov chains facilitates the application of probabilistic methods to very large logic synthesis and formal verification problems. In this paper we present symbolic algorithms to compute the steadystate probabilities for very large finite state machines (up to 10 27 states). These algorithms, based on Algebraic Decision Diagrams (ADDs)  an extension of BDDs that allows arbitrary values to be associated with the terminal nodes of the diagrams  determine the steadystate probabilities by regarding finite state machines as homogeneous, discreteparameter Markov chains with finite state spaces, and by solving the corresponding ChapmanKolmogorov equations. We first consider finite state machines with state graphs composed of a single terminal strongly connected component; for this type of systems we have implemented two solution techniques: One is based on the GaussJacobi iteration, the other one is based on simple matrix multiplication. Then we...
Parallelizing the Murφ verifier
 Computer Aided Verification. 9th International Conference
, 1997
"... With the use of state and memory reduction techniques in verification by explicit state enumeration, runtime becomes a major limiting factor. We describe a parallel version of the explicit state enumeration verifier Murφ for distributed memory multiprocessors and networks of workstations that is ba ..."
Abstract

Cited by 73 (0 self)
 Add to MetaCart
With the use of state and memory reduction techniques in verification by explicit state enumeration, runtime becomes a major limiting factor. We describe a parallel version of the explicit state enumeration verifier Murφ for distributed memory multiprocessors and networks of workstations that is based on the message passing paradigm. In experiments with three complex cache coherence protocols, parallel Murφ shows close to linear speedups, which are largely insensitive to communication latency and bandwidth. There is some slowdown with increasing communication overhead, for which a simple yet relatively accurate approximation formula is given. Techniques to reduce overhead and required bandwidth and to allow heterogeneity and dynamically changing load in the parallel machine are discussed, which we expect will allow good speedups when using conventional networks of workstations.
Efficient BDD Algorithms for FSM Synthesis and Verification
 In IEEE/ACM Proceedings International Workshop on Logic Synthesis, Lake Tahoe (NV
, 1995
"... We describe a set of BDD based algorithms for efficient FSM synthesis and verification. We establish that the core computation in both synthesis and verification is forming the image and preimage of sets of states under the transition relation characterizing the design. To make these steps as effic ..."
Abstract

Cited by 73 (3 self)
 Add to MetaCart
(Show Context)
We describe a set of BDD based algorithms for efficient FSM synthesis and verification. We establish that the core computation in both synthesis and verification is forming the image and preimage of sets of states under the transition relation characterizing the design. To make these steps as efficient as possible, we address BDD variable ordering, use of partitioned transition relations, and use of clustering. We provide an integrated set of algorithms and give references and comparisons with previous work. We report experimental results on a series of seven industrial examples containing from 28 to 172 binary valued latches. 1 Introduction The advent of modern VLSI CAD tools has radically changed the process of designing digital systems. The first CAD tools automated the final stages of design, such as placement and routing. As the low level steps became better understood, the focus shifted to the higher stages. In particular logic synthesis, the science of optimizing designs (for ...
Quantitative Solution of OmegaRegular Games
"... We consider twoplayer games played for an infinite number of rounds, with ωregular winning conditions. The games may be concurrent, in that the players choose their moves simultaneously and independently, and probabilistic, in that the moves determine a probability distribution for the successor s ..."
Abstract

Cited by 62 (18 self)
 Add to MetaCart
We consider twoplayer games played for an infinite number of rounds, with ωregular winning conditions. The games may be concurrent, in that the players choose their moves simultaneously and independently, and probabilistic, in that the moves determine a probability distribution for the successor state. We introduce quantitative game µcalculus, and we show that the maximal probability of winning such games can be expressed as the fixpoint formulas in this calculus. We develop the arguments both for deterministic and for probabilistic concurrent games; as a special case, we solve probabilistic turnbased games with ωregular winning conditions, which was also open. We also characterize the optimality, and the memory requirements, of the winning strategies. In particular, we show that while memoryless strategies suffice for winning games with safety and reachability conditions, Büchi conditions require the use of strategies with infinite memory. The existence of optimal strategies, as opposed to εoptimal, is only guaranteed in games with safety winning conditions.
A Compositional Realtime Semantics of STATEMATE Designs
, 1998
"... Introduction This paper presents a reference semantics for a verification tool currently under development allowing to verify temporal properties of embedded control systems modelled using the StateMate system. The semantics reported differs from others reported in the literature [24] by faithfully ..."
Abstract

Cited by 59 (6 self)
 Add to MetaCart
Introduction This paper presents a reference semantics for a verification tool currently under development allowing to verify temporal properties of embedded control systems modelled using the StateMate system. The semantics reported differs from others reported in the literature [24] by faithfully modelling the semantics as supported in the StateMate simulation tool. It differs from the recent paper by Harel and Naamad [8] by providing a compositional semantics, a prerequisite for the support of compositional verification methods, and by the degree of mathematical rigour. We use a variant of synchronous transition systems introduced by Manna and Pnueli [18] as base model for our semantics. The StateMate modelling language constructs covered in this paper are Activity charts , modelling the functional decomposition of a design into subunits called activities
Automatic Generation of Functional Vectors Using The Extended Finite State Machine Model
 ACM Trans. on design Automation of Electronic Systems
, 1996
"... We present a method of automatic generation of functional vectors for sequential circuits. These vectors can be used for design verification, manufacturing testing or power estimation. A highlevel description of the circuit, in VHDL or C, is assumed available. Our method automatically transforms th ..."
Abstract

Cited by 59 (2 self)
 Add to MetaCart
(Show Context)
We present a method of automatic generation of functional vectors for sequential circuits. These vectors can be used for design verification, manufacturing testing or power estimation. A highlevel description of the circuit, in VHDL or C, is assumed available. Our method automatically transforms the highlevel description, in VHDL or C, of a circuit into an extended finite state machine (EFSM) model that is used to generate functional vectors. The EFSM model is a generalization of the traditional state machine model. It is a compact representation of models with local data variables and preserves many nice properties of a traditional state machine model. The theoretical background of the EFSM model will be addressed in this paper. Our method guarantees that the generated vectors cover every statement in the highlevel description at least once. Experimental results show that a set of comprehensive functional vectors for sequential circuits with more than a hundred flipflops can be ge...
Improved Probabilistic Verification by Hash Compaction
 In Advanced Research Working Conference on Correct Hardware Design and Verification Methods
, 1995
"... . We present and analyze a probabilistic method for verification by explicit state enumeration, which improves on the "hashcompact" method of Wolper and Leroy. The hashcompact method maintains a hash table in which compressed values for states instead of full state descriptors are stored. ..."
Abstract

Cited by 46 (7 self)
 Add to MetaCart
(Show Context)
. We present and analyze a probabilistic method for verification by explicit state enumeration, which improves on the "hashcompact" method of Wolper and Leroy. The hashcompact method maintains a hash table in which compressed values for states instead of full state descriptors are stored. This method saves space but allows a nonzero probability of omitting states during verification, which may cause verification to miss design errors (i.e. verification may produce "false positives"). Our method improves on Wolper and Leroy's by calculating the hash and compressed values independently, and by using a specific hashing scheme that requires a low number of probes in the hash table. The result is a large reduction in the probability of omitting a state. Hence, we can achieve a given upper bound on the probability of omitting a state using fewer bits per compressed state. For example, we can reduce the number of bytes stored for each state from the eight recommended by Wolper and Leroy to o...
Automatic Verification of the SCI Cache Coherence Protocol
 In Correct Hardware Design and Verification Methods: IFIP WG10.5 Advanced Research Working Conference Proceedings
, 1995
"... . This paper describes an ongoing effort to verify the cache coherence protocol of the IEEE/ANSI Standard for Scalable Coherent Interface using the Mur' verification system. A model of the typical set protocol was constructed in the Mur' description language. This model was augmented with ..."
Abstract

Cited by 45 (16 self)
 Add to MetaCart
(Show Context)
. This paper describes an ongoing effort to verify the cache coherence protocol of the IEEE/ANSI Standard for Scalable Coherent Interface using the Mur' verification system. A model of the typical set protocol was constructed in the Mur' description language. This model was augmented with a specification of properties necessary for cache coherence. The Mur' verification system automatically checks if all reachable states in the model satisfy the given specification. Although verification is still under way, we have already found several errors in the Ccode defining the protocol. Finally, we elucidate the experiences gained in the verification project. 1 Introduction The IEEE/ANSI Standard for Scalable Coherent Interface (SCI) includes a cache coherence protocol for distributed sharedmemory multiprocessors. Designing a complex protocol  like this cache coherence protocol  is a challenging and difficult task. It is very hard for a designer to predict all possible interactions amon...