Abstmct-The Sees&t @ software visualization system allows one to analyze up to 50 000 lines of code simultaneously by mapping each line of code into a thin row. The color of each row indicates a statistic of interest, e.g., red rows are those most recently changed, and blue are those least recently changed. Seesoft displays data derived from a variety of sources, such as- version control systems that track the age, programmer, and purpose of the code, e.g., control ISDN lamps, fix hug in call forwarding; * static analyses, e.g., locations where functions are called; and l dynamic analyses, e.g., profiling. By means of direct manipulation and high interaction graphics, the user can manipulate this reduced repnzsentation of the code in order to find interesting patterns. Further insight is obtained by using additional windows to display the actual code. Potential applications for Seesoft include discovery, project management, code tuning, and analysis of development methodologies. Index Terms<hange management systems, code browsing, in-teractive graphics, line oriented statistics, scientific visualization. A

: -- An ongoing research project involves the design and evaluation of a software system for simulating parallel computers. A major goal in the development of this system was to avoid the high overhead associated with the conventional instruction-level simulation of sequential computers, but to retain the accuracy of that technique derived from its use of the execution of real programs. The resulting system is program-driven, but the overhead is significantly reduced by profiling the program to get timing estimates for its basic blocks, which are then used at run time to generate process execution times dynamically while avoiding a detailed emulation of each instruction's execution. A number of experiments dealing with message-passing computer systems have been performed in order to determine the level of accuracy that can be expected from its performance predictions and to measure its overhead. Index Terms -- Architecture models, efficiency, parallel computers, parallel programs, per...

This paper describes and evaluates an efficient execution-driven technique for the simulation of multiprocessors that includes the simulation of system memory and is driven by real program workloads. The technique produces correctly interleaved address traces at run time without disk access overhead or hardware support, allowing accurate simulation of the effects of a variety of architectural alternatives on programs. We have implemented a simulator based on this technique that offers substantial advantages in terms of reduced time and space overheads when compared to instruction-driven or trace-driven simulation techniques, without significant loss of accuracy. The paper presents the results of several validation experiments used to quantify the accuracy and efficiency of the simulator for sequential, distributed, and shared-memory multiprocessors, and several parallel programs. These experiments show that prediction errors of less than 5% compared to actual execution times and overhe...

Simulation using address reference traces is one of the primary methods for the performance evaluation of the memory hierarchy of computer systems. In this paper we survey the techniques used in such a simulation. In both the uniprocessor and shared-memory multiprocessor cases, the issues can be divided into trace collection, trace storage, and trace usage. Trace collection can employ several hardware or software methods. Common concerns are that the collection method capture all of the address references of interest, that the execution overhead of the collection method is not excessive, and that the trace is of adequate length. The increasing size of caches heightens the adequate length concern. Trace storage is of concern because of the large size of traces. Techniques for trace compression and trace reduction have been developed. Trace usage is of concern because of the length of a simulation. Under some circumstances it is possible to evaluate multiple cache sizes in a si...

Profiling under UNIX ® is done by inserting counters into programs either before compiling, during compiling, or during assembly. A fourth type of profiling involves monitoring the execution of a program, and gathering relevant statistics during the run. This paper looks at this method and an implementation of it, and discusses its advantages and disadvantages.

The number of design decisions for communication network hardware in message passing distributed memory systems is quite large, as illustrated by many different implemented and proposed designs. Many of the decisions are driven by, on one side, performance requirements of targeted applications for the parallel system, and on the other side, hardware implementation costs. To obtain cost effective communication hardware matching a certain application domain, use of a parallel architecture simulation framework is inevitable. The simulator presented here, named PARSE, offers a base for such a framework. It can accurately simulate a wide range of communication architectures and, unlike analytic communication models, does properly model all performance aspects. Changing parameters of simulated architectures is very flexible and the object oriented implementation of the simulator facilitates future extensions and enhancements. 1 Introduction Given the many different communication hardware de...

Structured testing, also known as basis path testing, is a methodology for software module testing based on the cyclomatic complexity measure of McCabe. In this dissertation, we analyze the theoretical properties of structured testing, describe the implementation of a system to support structured testing, empirically evaluate the error detection performance of structured testing, and extend the structured testing approach to cover integration testing. We exhibit a class of programs with unbounded complexity for which the structured testing approach is both necessary and sufficient to ensure correctness, and place structured testing in a hierarchy with other structural testing criteria. We also discuss Weyuker's axioms for testing criteria, and show that a variant of structured testing in which only executable paths are considered satisfies those axioms. We describe an automated system to support structured testing for the C language. We present a technique for assessing and improving a...

Proteus is a high-performance simulator for MIMD multiprocessors. It is fast, accurate, and flexible: it is one to two orders of magnitude faster than comparable simulators, it can reproduce results from real multiprocessors, and it is easily configured to simulate a wide range of architectures. Proteus provides a modular structure that simplifies customization and independent replacement of parts of architecture. There are typically multiple implementations of each module that provide different combinations of accuracy and performance; users pay for accuracy only when and where they need it. Finally, Proteus provides repeatability, nonintrusive monitoring and debugging, and integrated graphical output, which result in a development environment superior to those available on real multiprocessors. Keywords: Execution-driven simulation, parallel algorithm design and evaluation, parallel architecture, parallel debugging c fl Massachusetts Institute of Technology 1991 This is an electroni...

VHDL is the one of the most important and widely used hardware description languages at this time. The increase in size and complexity of VHDL models necessitates the use of parallel and distributed algorithms to obtain acceptable simulation performance. We have investigated the use of optimistic distributed algorithms with VHDL simulation. Using an optimistic algorithm with VHDL introduces some major problems which can only be solved at some cost. With our simulation environment we obtain speedups of around four for a medium-sized benchmark. We expect that the optimisation of our environment and partitioning, and the use of larger benchmarks will lead to higher speedups, which makes it worthwhile to investigate this approach further. 1 Introduction The design of todays complex digital systems requires the use of a hardware description and simulation language. VHDL has emerged as one of the most widely used hardware description languages, and has become a world-wide accepted standard....

lcc is a new retargetable compiler for ANSI C. Versions for the VAX, Motorola 68020, SPARC, and MIPS are in production use at Princeton University and at AT&T Bell Laboratories. With a few exceptions, little about lcc is unusual --- it integrates several well engineered, existing techniques --- but it is smaller and faster than most other C compilers, and it generates code of comparable quality. lcc's target-independent front end performs a few simple, but e#ective, optimizations that contribute to good code; examples include simulating register declarations and partitioning switch statement cases into dense tables. It also implements target-independent function tracing and expression-level profiling. Introduction Reprinted from SIGPLAN Notices 26, 10 (Oct. 1991), 29--43. Copyright 1991, Association for Computing Machinery, Inc., reprinted by permission. lcc is a new retargetable compiler for ANSI C [2]. It has been ported to the VAX, Motorola 68020, SPARC, and MIPS R3000, a...